Julien Lamoureux
Steven J. E. Wilton
Abstract
FPGA clock networks consume a significant amount of power, since they toggle every clock cycle and must be flexible enough to implement the clocks for a wide range of different applications. The efficiency of FPGA clock networks can be improved by reducing this flexibility; however, reducing the flexibility introduces stricter constraints during the clustering and placement stages of the FPGA CAD flow. These constraints can reduce the overall efficiency of the final implementation. This article examines the trade-off between the power consumption and flexibility of FPGA clock networks.
Specifically, this article makes three contributions. First, it presents a new parameterized clock-network framework for describing and comparing FPGA clock networks. Second, it describes new clock-aware placement techniques that are needed to find a legal placement satisfying the constraints imposed by the clock network. Finally, it performs an empirical study to examine the trade-off between the power consumption of the clock network and the impact of the CAD constraints for a number of different clock networks with varying amounts of flexibility.
The results show that the techniques used to produce a legal placement can have a significant influence on power and the ability of the placer to find a legal solution. On average, circuits placed using the most effective techniques dissipate 5% less overall energy and are significantly more likely to be legal than circuits placed using other techniques. Moreover, the results show that the architecture of the clock network is also important. On average, FPGAs with an efficient clock network are up to 14.6% more energy efficient compared to other FPGAs.
- ACTEL. 2007. ProASIC3 flash family FPGAs datasheet: Device architecture (Jan.).Google Scholar
- ALTERA. 2005. Stratix II Device Handbook 1. Chapter 2 (Mar.).Google Scholar
- ALTERA. 2006. Stratix III Device Handbook 1. Chapter 6 (Nov.).Google Scholar
- Bakolgu, H. B. 1990. Machine organization and rent's rule. In Circuits, Interconnections, and Packaging for VLSI. Addison-Wesley, Reading, MA.Google Scholar
- Betz, V., Rose, J., and Marquardt, A. 1999. Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic. Google ScholarDigital Library
- Brynjolfson, I. and Zilic, Z. 2000. Dynamic clock management for low-power applications in FPGAs. In Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), 139--142.Google Scholar
- Edahiro, M. and Lipton, R. J. 1996. Clock buffer placement algorithm for wire-delay-dominated timing model. In Proceedings of the Great Lakes Symposium on VLSI, 143--147. Google ScholarDigital Library
- Friedman, E. G. 2001. Clock distribution networks in synchronous digital integrated circuits. Proc. IEEE 89, 5 (May), 665--692.Google ScholarCross Ref
- George, V., Zang, H., and Rabaey, J. 1999. The design of a low-energy FPGAs. In Proceedings of the International Symposium on Low-Power Electronic Design (ISLPED), 188--193. Google ScholarDigital Library
- Lamoureux, J., and Wilton, S. J. E. 2005. On the interaction between power-aware computer-aided design algorithms for field-programmable gate arrays. J. Low Power Electron. 1, 2, 119--132.Google ScholarCross Ref
- Lamoureux, J. and Wilton, S. J. E. 2006. FPGA clock network architecture: Flexibility vs. area and power. In Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 101--108. Google ScholarDigital Library
- Lamoureux, J. and Wilton, S. J. E. 2007. Clock-Aware placement for FPGAs. In Proceedings of the International Conference on Field-Programmable Logic and Applications (FPL).Google Scholar
- Landman, B. S. and Russo, R. L. 1971. On a pin versus block relationship for partitions of logic graphs. IEEE Trans. Comput. C-20, 12, 1469--1479. Google ScholarDigital Library
- Li, F., Chen, D., He, L., and Cong, J. 2003. Architecture evaluation for power-efficient FPGAs. In Proceedings of the International Symposium on Field-Programmable Gate Arrays (FPGA), 175--184. Google ScholarDigital Library
- Nakamura, S. and Masson, G. M. 1982. Lower bounds on crosspoints in concentrators. IEEE Trans. Comput. 31, 12, 1173--1178. Google ScholarDigital Library
- Poon, K. K. W. and Wilton, S. J. E. 2005. A detailed power model for field-programmable gate arrays. ACM Trans. Des. Autom. Electron. Syst.10, 2 (Apr.), 279--302. Google ScholarDigital Library
- Natesan, V. and Bhatia, D. 1996. Clock-Skew constrained cell placement. In Proceedings of the International Conference on VLSI Design, 146--149. Google ScholarDigital Library
- Schabas, K. and Brown, S. D. 2003. Using logic duplication to improve performance in FPGAs. In Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 136--142. Google ScholarDigital Library
- Tuan, T., Kao, S., Rahman, A., Das, S., and Trimberger, S. 2006. A 90nm low-power FPGA for battery-powered applications. In Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 3--11. Google ScholarDigital Library
- XILINX. 2007. Virtex-5 User Guide. Chapter 2 (Feb).Google Scholar
- Zhu, K. and Wong, D. F. 1997. Clock skew minimization during FPGA placement. IEEE Trans. Comput. Aided Des. Integr. Circ. 16, 4 (Apr.), 376--385. Google ScholarDigital Library
Index Terms
- On the trade-off between power and flexibility of FPGA clock networks
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