- 1.P. R. Panda, N. D. Dutt, and A. Nicolau. "Data Cache Sizing for Embedded Processor Applications." Technical Report ICS-TR-97-31, University of California, Irvine, June 1997.Google Scholar
- 2.P. R. Panda, N. D. Dutt, and A. Nicolau. "Architectural Exploration and Optimization of Local Memory in Embedded Systems." International Symposium on System Synthesis (ISSS 97), Antwerp, Sept. 1997. Google ScholarDigital Library
- 3.M. B. Kamble and K. Ghose, "Analytical Energy Dissipation Models for Low Power Caches", International Symposium on Low Power Electronics and Design, 1997. Google ScholarDigital Library
- 4.S. E. Wilton and N. Jouppi, "An Enhanced Access and Cycle Time Model for On-chip Caches", Digital Equipment Corporation Western Research Lab, Tech. Report 93/5, 1994.Google Scholar
- 5.C. Su and A. Despain, "Cache Design Trade-offs for Power and Performance Optimization: A Case Study", International Symposium on Low Power Electronics and Design, pages 63-68, 1995. Google ScholarDigital Library
- 6.P. Hicks, M. Walnock, R. M. Owens, "Analysis of Power Consumption in Memory Hierarchies", International Symposium on Low Power Electronics and Design, pages 239-242, 1997. Google ScholarDigital Library
- 7.A. Thordarson, "Comparison of Manual and Automatic Behavioral Synthesis of MPEG Algorithm", Master' s thesis, University of California, Irvine, 1995.Google Scholar
- 8.D. Kirovski, C. Lee, M. Potkonjak, and W. Mangione- Smith, "Application-Driven Synthesis of Core-based Systems", In Proceedings of the IEEE/ACM International Conference on Computer Aided Design, pages 104-107, San Jose, CA, November 1997. Google ScholarDigital Library
- 9.M. E. Wolf and M. Lain. "A Data Locality Optimizing Algorithm." In proceedings of the SIGPLAN'9 Conference on Programming Language Design and Implementation, pages 30-44, June 1991. Google ScholarDigital Library
- 10.J. L. Hennessy and D. A. Patterson, "Computer Architecture A Quantitative Approach", 2nd edition Morgan Kaufman Publishers, 1996. Google ScholarDigital Library
- 11.J. Edler and M. D. Hill, " Dinero IV Trace-Driven Uniprocessor Cache Simulator", web site: http://www.neci.nj.nec.com/homepages/edler/d4 or http://www.cs.wisc.edu/Nmarkhill/DineroIV.Google Scholar
Index Terms
- Memory exploration for low power, embedded systems
Recommendations
An integrated memory-disk system with buffering adapter and non-volatile memory
Next generation non-volatile memory devices are promising replacements for DRAM and Flash memories for mobile devices because of their energy efficiency and non-volatile characteristics. In this paper, we propose a new memory hierarchy system for next-...
Exploring latency-power tradeoffs in deep nonvolatile memory hierarchies
CF '12: Proceedings of the 9th conference on Computing FrontiersTo handle the demand for very large main memory, we are likely to use nonvolatile memory (NVM) as main memory. NVM main memory will have higher latency than DRAM. To cope with this, we advocate a less-deep cache hierarchy based on a large last-level, ...
A Low Power TLB Structure for Embedded Systems
We present a new two-level TLB (translationlook-aside buffer) architecture that integrates a 2-waybanked filter TLB with a 2-way banked main TLB. Theobjective is to reduce power consumption in embeddedprocessors by distributing the accesses to TLB ...
Comments