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"Design of A Bit-Serial Artificial Neuron VLSI Architecture with Early ..."

Yun-Nan Chang, Guan-Jhen Chen (2019)

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DOI: 10.23919/ELINFOCOM.2019.8706444

access: closed

type: Conference or Workshop Paper

metadata version: 2019-12-05

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Yun-Nan Chang, Guan-Jhen Chen:
Design of A Bit-Serial Artificial Neuron VLSI Architecture with Early Termination. ICEIC 2019: 1-3

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