hftrx/cs4272.c at master · imaSoft/hftrx · GitHub

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
/* $Id$ */
//
//
// Ïðîåêò HF Dream Receiver (ÊÂ ïðè¸ìíèê ìå÷òû)
// àâòîð Ãåíà Çàâèäîâñêèé mgs2001@mail.ru
// UA1ARN
//
#include "hardware.h"
#include "board.h"

#include "spifuncs.h"

#include "./formats.h"

#if defined(CODEC2_TYPE) && (CODEC2_TYPE == CODEC_TYPE_CS4272)

#include "audio.h"

//
// Óïðàâëåíèå êîäåêîì CS4272
//
// Â slave mode äàííûé êîäåê èçìåíÿåò âûäàâàåòìûå äàííûå ïî ñïàäàþùåì ôðîíòó ñèãíàëà SCLK.
// Ñóäÿ ïî äîêóìåíòàöèè, îæèäàåò ÷òî ìàñòåð òàê æå èçìåíÿåò âûäàâàåìûå äàííûå ïî ñïàäàþùåìó ôðîíòó SCLK.
//

#define CS4272_SPIMODE		SPIC_MODE3

#define CS4272_ADDRESS_W	0x20	// I2C address: 0x20 or 0x22	- depend on adress pin state
									// Also used as SPI prefix byte
#define CS4272_ADDRESS_R	(CS4272_ADDRESS_W + 1)

//memory address pointers
#define MODE_CONTROL_1 0x1 //memory address pointer for modeControl1
#define DAC_CONTROL 0x2 //memory address pointer for DACControl
#define DAC_VOLUME_AND_MIXING 0x3 //memory address pointer for DACVolume and Mixing control
#define DAC_VOLUME_A 0x4 //memory address pointer for DACVolumeA
#define DAC_VOLUME_B 0x5 //memory address pointer for DACVolumeB
#define ADC_CONTROL 0x6 //memory address pointer for ADC Control
#define MODE_CONTROL_2 0x7 //memory address pointer for ModeControlTwo


#define ADC_CONTROL_HPF_DISABLE_B 0x01
#define ADC_CONTROL_HPF_DISABLE_A 0x02
#define ADC_CONTROL_I2S 0x10
#define ADC_CONTROL_DITHER16 0x20

#define MODE_CONTROL_2_PDN 0x01
#define MODE_CONTROL_2_CPEN 0x02
#define MODE_CONTROL_2_LOOP 0x10

// òàê êàê íà ïðè¸ìå èñïîëüçóåòñÿ 32-áèòíûé ôðåéì, ìîæíî èñïîëüçîâàòü òîëüêî
// ôîðìàò left justified - òàê êàê êîäåê "íå çíàåò" êîãäà çàêîí÷èòñÿ ôðåéì.
enum { USE_I2S = 0 };	// 0 = left justified, 1 = phillips I2S


static void cs4272_setreg(
	uint_fast8_t mapv,	// Memory Address Pointer
	uint_fast8_t datav
	)
{
#if CODEC_TYPE_CS4272_STANDALONE
	return;
#elif CODEC_TYPE_CS4272_USE_SPI
	// êîäåê óïðàâëÿåòñÿ ïî SPI
	const spitarget_t target = targetcodec2;	/* addressing to chip */

	spi_select(target, CS4272_SPIMODE);
	spi_progval8_p1(target, CS4272_ADDRESS_W);		// Chip Aaddress, D0=0: write
	spi_progval8_p2(target, mapv);		// LSB=b8 of datav
	spi_progval8_p2(target, datav);
	spi_complete(target);
	spi_unselect(target);

#else
	// êîäåê óïðàâëÿåòñÿ ïî I2C
	i2c_start(CS4272_ADDRESS_W);
	i2c_write(mapv);
	i2c_write(datav);
	i2c_waitsend();
	i2c_stop();

	// resd back for test
	/*
	uint_fast8_t v1;

	i2c_start(CS4272_ADDRESS_R);
	//i2c_write(mapv);
	i2c_read(& v1, I2C_READ_ACK_NACK);

	debug_printf_P(PSTR("cs4272: a=%02x, v1=%02x (%02x)\n"), mapv, v1, datav);
	*/
#endif
}

// MCLK äîëæåí óæå ïîäàâàòüñÿ â ìîìåíò èíèöèàëèçàöèè
static void cs4272_initialize_fullduplex(void)
{
	board_codec2_nreset(1);	// Âûñòàâèòü ñèãíàë ñáðîñà
	board_update();
	local_delay_ms(2);
	board_codec2_nreset(0);	// ñíÿòü ñèãíàë ñáðîñà
	board_update();

#if CODEC_TYPE_CS4272_STANDALONE
	return;
#endif /* CODEC_TYPE_CS4272_STANDALONE */

	    //CODEC START SEQUENCE
    cs4272_setreg(MODE_CONTROL_2, MODE_CONTROL_2_PDN | MODE_CONTROL_2_CPEN);// write 0x03 to register 0x07 within 10ms of bringing RST_bar high
    cs4272_setreg(MODE_CONTROL_1,
		(USE_I2S << 0) |		/* DAC_DIF2:DAC_DIF1:DAC_DIF0 format LJ/I2S */
		(0U << 4) |		/* ratio select: Slave Mode, MCLK/LRCK=256, SCLK/LRCK=32, 64, 128 */
		0x00
		);

    cs4272_setreg(DAC_CONTROL,
		//(2U << 4) |	// De-Emphasis Control (Bits 5:4), 2: 48 kHz de-emphasis
		//(1U << 6) |	// Interpolation Filter Select (Bit 6), 0: fast roll off filter
		0);
    cs4272_setreg(DAC_VOLUME_AND_MIXING,	// DACVolume and Mixing control
		(1U << 6) |	// A=B
		(6U << 0) |	// ATAPI mixing control
		//(9U << 0) |	// ATAPI mixing control reverse
		0);
    cs4272_setreg(DAC_VOLUME_A, 0);	// set attenuation
    cs4272_setreg(DAC_VOLUME_B, 0);	// set attenuation

    cs4272_setreg(ADC_CONTROL,
		(USE_I2S << 4) |		/* ADC_DIF: format LJ/I2S */
		//(1 * ADC_CONTROL_HPF_DISABLE_B) |
		//(1 * ADC_CONTROL_HPF_DISABLE_A) |
		//0x04 |	// MUTE B
		//0x08 |	// MUTE A
		0);

    cs4272_setreg(MODE_CONTROL_2, MODE_CONTROL_2_CPEN);

#if 1
	// calibration
	local_delay_ms(200);
    cs4272_setreg(ADC_CONTROL,
		(USE_I2S << 4) |		/* ADC_DIF: format LJ/I2S */
		(1 * ADC_CONTROL_HPF_DISABLE_B) |
		(1 * ADC_CONTROL_HPF_DISABLE_A) |
		//0x04 |	// MUTE B
		//0x08 |	// MUTE A
		0);
#endif
}


const codec2if_t * board_getfpgacodecif(void)
{
	static const char codecname [] = "CS4272";

	/* Èíòåðôåéñ öïðàâëåíèÿ êîäåêîì */
	static const codec2if_t ifc =
	{
		cs4272_initialize_fullduplex,
		codecname
	};

	return & ifc;
}

#endif /* defined(CODEC2_TYPE) && (CODEC2_TYPE == CODEC_TYPE_CS4272) */