Jun Yang
Abstract
By analyzing the behavior of a set of benchmarks, we demonstrate that a small number of distinct values tend to occur very frequently in memory. On an average, only eight of these frequent values were found to occupy 48% of memory locations for the benchmarks studied. In addition, we demonstrate that the identity of frequent values remains stable over the entire execution of the program and these values are scattered fairly uniformly across the allocated memory. We present three different algorithms for finding frequent values and experimentally demonstrate their effectiveness. Each of these algorithms is designed to suit a different application scenario. Since the contents of memory exhibit frequent value locality, it is expected that frequent values will be observed in data streams that flow across different points in the memory hierarchy. We exploit this observation for developing two low-power designs: a low-power level-one data cache and a low-power external data bus. In each of these applications a different form of encoding of frequent values is employed to obtain a low-power design. We also experimentally demonstrate the effectiveness of these designs.
- Benini, L., Macii, A., Macii, E., Poncino, M., and Scarsi, R. 1999. Synthesis of low-overhead interfaces for power-efficient communication over wide buses. In Proceedings of the Design Automation Conference. ACM, New York, 128--133. Google Scholar
- Brooks, D., Tiwari, V., and Martonosi, M. 2000. Wattch: A framework for architectural-level power analysis and optimizations. In Proceedings of the 27th International Symposium on Computer Architecture. ACM/IEEE, New York, 83--94. Google Scholar
- Calder, B., Feller, P., and Eustace, A. 1997. Value profiling. In Proceedings of the 30th International Symposium on Microarchitecture. IEEE/ACM, New York, 259--269. Google Scholar
- Gabbay, F. and Mendelson, A. 1997. Can program profiling support value prediction? In Proceedings of the 30th International Symposium on Microarchitecture. IEEE/ACM, New York, 270--280. Google Scholar
- Ghose, K. and Kamble, M. 1999. Reducing Power in Superscalar Processor Caches using Subbanking, Multiple Line Buffers, and Bit Line Segmentation. In Proceedings of the 1999 International Symposium on Low Power Electronics and Design. IEEE/ACM, New York, 70--75. Google Scholar
- Huang, M., Renau, J., Yoo, S. M. and Torrellas, J. 2001. L1 data cache decomposition for energy efficiency. In Proceedings of the 2001 International Symposium on Low Power Electronics and Design. IEEE/ACM, New York, 10--15. Google Scholar
- Larin, S. Y. 2000. Exploiting program redundancy to improve performance. Ph.D. Thesis. ECE Dept., North Carolina State University, Raleigh, NC. Google Scholar
- Lipasti, M. H., Wilkerson, C. B., and Shen, J. P. 1996. Value locality and load value prediction. In Proceedings of the Seventh International Conference on Architectural Support for Programming Languages and Operating Systems. ACM, New York, 138--147. Google Scholar
- Onder, S. and Gupta, R. 1998. Automatic generation of microarchitecture simulators. In Proceedings of the International Conference on Computer Languages. IEEE Press, New York, 80--89. Google Scholar
- Reinman, G. and Jouppi, N. 1999. An integrated cache timing and power model. Tech. Rep. Western Research Lab.Google Scholar
- Stan, M. R. and Burleson, W. P. 1995. Bus-invert coding for low power I/O. IEEE Transactions on VLSI Systems 3, 1 (Mar.), 49--58. Google Scholar
- Villa, L., Zhang, M., and Asanovic, K. 2000. Dynamic zero compression for cache energy reduction. In Proceedings of the 33d Annual International Symposium on Microarchitecture. IEEE/ACM, 214--210. Google Scholar
- Zhang, Y., Yang, J., and Gupta, R. 2000. Frequent value locality and value-centric data cache design. In Proceedings of the 9th International Conference on Architectural Support for Programming Languages and Operating Systems. ACM, New York, 150--159. Google Scholar
Index Terms
- Frequent value locality and its applications
Recommendations
Frequent value locality and value-centric data cache design
Special Issue: Proceedings of the ninth international conference on Architectural support for programming languages and operating systems (ASPLOS '00)By studying the behavior of programs in the SPECint95 suite we observed that six out of eight programs exhibit a new kind of value locality, the frequent value locality, according to which a few values appear very frequently in memory locations and are ...
Value locality and load value prediction
Since the introduction of virtual memory demand-paging and cache memories, computer systems have been exploiting spatial and temporal locality to reduce the average latency of a memory reference. In this paper, we introduce the notion of value locality, ...
Frequent value locality and value-centric data cache design
By studying the behavior of programs in the SPECint95 suite we observed that six out of eight programs exhibit a new kind of value locality, the frequent value locality, according to which a few values appear very frequently in memory locations and are ...
Comments