Abstract
CAD tool designers are always searching for more benchmark circuits to stress their software. In this article we present a heuristic method to generate benchmark circuits specially suited for incremental place-and-route tools. The method removes part of a real circuit and replaces it with an altered version of the same circuit to mimic an incremental design change. The alteration consists of two steps: mutate followed by perturb. The perturb step exactly preserves as many circuit characteristics as possible. While perturbing, reproduction of interconnect locality, a characteristic that is difficult to measure reliably or reproduce exactly, is controlled using a new technique, ancestor depth control (ADC). Perturbing with ADC produces circuits with postrouting properties that match the best techniques known to-date. The mutate step produces targetted mutations resulting in controlled changes to specific circuit properties (while keeping other properties constant). We demonstrate one targetted mutation heuristic, scale, to significantly change circuit size with little change to other circuit characteristics. The method is simple enough for inclusion in a CAD tool directly, and fast enough for use in on-the-fly benchmark generation.
- Betz, V., Rose, J., and Marquardt, A. 1999. Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic, Boston, MA. Google ScholarDigital Library
- Cong, J. and Sarrafzadeh, M. 2000. Incremental physical design. In Proceedings of the International Symposium on Physical Design (ISPD). ACM Press, New York, 84--92. Google ScholarDigital Library
- Coudert, O., Cong, J., Malik, S., and Sarrafzadeh, M. 2000. Incremental CAD. In Proceedings of the IEEE/ACM International Conference on Computer Aided Design (ICCAD), 236--243. Google ScholarDigital Library
- Darnauer, J. and Dai, W. 1996. A method for generating random circuits and its application to routability measurement. In Proceedings of the 4th ACM/CIGDA Internation Symposium on FPGAs. 66--72. Google ScholarDigital Library
- Ghosh, D., Kapur, N., Harlow, J. E., and Brglez, F. 1998. Synthesis of wiring signature-invariant equivalence class circuit mutants and applications to benchmarking. In Proceedings of the Design Automation and Test in Europe (DATE), 663--671. Google ScholarDigital Library
- Grant, D., Chin, S., and Lemieux, G. 2006. Semi-Synthetic circuit generation using graph monomorphism for testing incremental placement and incremental routing tools. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, 725--728.Google Scholar
- Grant, D. and Lemieux, G. 2006. Perturber: Semi-Synthetic circuit generation using ancestor control for testing incremental place and route. In Proceedings of the International Conference on Field Programmable Technology (FPT), Bangkok, Thailand.Google Scholar
- Hutton, M., Rose, J., and Corneil, D. 2002. Automatic generation of synthetic sequential benchmark circuits. IEEE Trans. Comput.-Aided Des. 21, 8, 928--940. Google ScholarDigital Library
- Hutton, M., Rose, J., Grossman, J. P., and Corneil, D. 1998. Characterization and parameterized generation of synthetic combinational circuits. IEEE Trans. Comput.-Aided Des. 17, 10, 985--996. Google ScholarDigital Library
- Kapur, N., Ghosh, D., and Brglez, F. 1997. Towards a new benchmarking paradigm in EDA: Analysis of equivalence class mutant circuit distributions. In Proceedings of the International Symposium on Physical Design (ISPD), 136--143. Google ScholarDigital Library
- Kundarewich, P. and Rose, J. 2004. Synthetic circuit generation using clustering and iteration. IEEE Trans. Comput.-Aided Des. 23, 6, 869--887. Google ScholarDigital Library
- Leong, D. 2006. Incremental placement for FPGAs. M.S. thesis, Department of Electrical and Computer Engineering, University of British Columbia.Google Scholar
- Marquardt, A., Betz, V., and Rose, J. 2000. Speed and area tradeoffs in cluster-based FPGA architectures. IEEE Trans. Very Large 8, 1, 84--93. Google ScholarDigital Library
- Pistorius, J., Legai, E., and Minoux, M. 1999. Generation of very large circuits to benchmark the partitioning of FPGAs. In Proceedings of the International Symposium on Physical Design (ISPD). ACM Press, New York, 67--73. Google ScholarDigital Library
- Singh, D. P. and Brown, S. D. 2002a. Incremental placement for layout-driven optimizations on FPGAs. In Proceedings of the IEEE/ACM International Conference on Computer-aided Design (ICCAD). ACM Press, New York, 752--759. Google ScholarDigital Library
- Singh, D. P. and Brown, S. D. 2002b. Integrated retiming and placement for field programmable gate arrays. In Proceedings of the 10th International Symposium on Field Programmable Gate Arrays (FPGA). ACM Press, New York, 67--76. Google ScholarDigital Library
- Singh, D. P., Manohararaja, V., and Brown, S. D. 2005. Incremental retiming for FPGA physical synthesis. In Proceedings of the 42nd ACM IEEE Design Automation Conference (DAC). ACM Press, New York, 433--438. Google ScholarDigital Library
- Stroobandt, D., Verplaetse, P., and van Campenhout, J. 2000. Generating synthetic benchmark circuits for evaluating CAD tools. IEEE Trans. Comput.-Aided Des. 19, 9, 1011--1022. Google ScholarDigital Library
- Tom, M. and Lemieux, G. 2005. Logic block clustering of large designs for channel-width constrained FPGAs. In Proceedings of the 42nd Annual Conference on Design Automation (DAC). ACM Press, New York, 726--731. Google ScholarDigital Library
- Verplaetse, P., van Campenhout, J., and Stroobandt, D. 2000. On synthetic benchmark generation methods. In Proceedings of the IEEE International Symposium on Circuits and Systems, Volume IV 4, 213--216.Google Scholar
Index Terms
- Perturb+mutate: Semisynthetic circuit generation for incremental placement and routing
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