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Virtually eliminating router bugs
2009
Proceedings of the 5th international conference on Emerging networking experiments and technologies - CoNEXT '09
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Software bugs in routers lead to network outages, security vulnerabilities, and other unexpected behavior. ...
Rather than simply crashing the router, bugs can violate protocol semantics, rendering traditional failure detection and recovery techniques ineffective. ...
Designing a Bug-Tolerant Router In this paper, we describe how to eliminate router bugs "virtually" (with use of virtualization technologies). ...
doi:10.1145/1658939.1658942
dblp:conf/conext/KellerYCR09
fatcat:s6e7y4vpfvapte36hwrzlp3oxq
Network Gateway Technology: The Issue of Redundancy towards Effective Implementation
2012
African Research Review
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Network gateway redundancy technology makes it possible for computer devices to have access to multiple exit and entry points in the network, thus, eliminates the problem of a single point failure in both ...
For instance, routers and multilayer switches can function as network gateways and eliminate the problem of a single point failure in the network. ...
When Router A recovers, it becomes the master virtual router again. ...
doi:10.4314/afrrev.v6i1.6
fatcat:acjewjovkjh65dpfkigaawlcwi
DiAMOND:Distributed alteration of messages for on-chip network debug
2014
2014 Eighth IEEE/ACM International Symposium on Networks-on-Chip (NoCS)
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We also provide relevant statistics for debugging, such as packet interactions and packet latencies, per router. ...
Our solution is coupled with a detection scheme consisting of small checkers that monitor execution and flag bugs. Upon bug detection, we analyze the debug information to reconstruct network traffic. ...
Finally, by comparing a packet's requested output port and output virtual channel within a router relative to the input port and input virtual channel of the downstream router, functional bugs in switch ...
doi:10.1109/nocs.2014.7008771
dblp:conf/nocs/Abdel-KhalekB14
fatcat:6mcsz5ql35ahdazrtpdfevxnpy
Post-silicon platform for the functional diagnosis and debug of networks-on-chip
2014
ACM Transactions on Embedded Computing Systems
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Each router has 5 ports, 2 virtual channels, and 8 flit buffers. ...
The example router has five input ports, with each including two virtual channel buffers and an input virtual channel control logic. ...
doi:10.1145/2567936
fatcat:danvptshjnfrzen6f5rblc3cta
Approximating checkers for simulation acceleration
2012
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)
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To this end, checkers must be transformed into synthesizable, compact logic blocks with bug-detection capabilities similar to that of their software counterparts. ...
We present a general checker taxonomy, propose a range of approximation techniques based on a checker's characteristic and provide metrics for evaluating its bug detection capabilities. ...
2,928
782
73.3
calc3 reg file
eliminate
7,945
1,031
87
calc3 checker
combined
20,473
8,565
58.2
router input+output state redux
3,764
2,664
29.2
router flow
signatures
146,910
56,983 ...
doi:10.1109/date.2012.6176449
dblp:conf/date/MammoCPNZMB12
fatcat:3cydj6wyprfdrgusz2tcqqc36u
Towards understanding bugs in open source router software
2010
Computer communication review
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In this paper, we study router bugs found in two widely-used open-source router implementations. ...
Building an understanding of bugs in open-source router software is a first step towards addressing these problems. ...
By doing the above steps, we eliminated around 63% of bug reports from Quagga, XORP and the Linux IP stack. ...
doi:10.1145/1823844.1823849
fatcat:alfjbolnlrhcbb6o5k6wwn2u3m
Formally enhanced runtime verification to ensure NoC functional correctness
2011
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture - MICRO-44 '11
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Formal verification, due to its scalability limitations, is used to verify the smaller modules, such as individual router components. ...
If a bug is detected, flagged by missed packet arrivals, a recovery mechanism delivers the in-flight data safely to the intended destination via the checker network. ...
In the context of an individual router, the interactions between the virtual channels are handled by RC, VA and SA units. ...
doi:10.1145/2155620.2155668
dblp:conf/micro/ParikhB11
fatcat:co2magm7pbg7bgptip4ern5h4e
Functional correctness for CMP interconnects
2011
2011 IEEE 29th International Conference on Computer Design (ICCD)
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If a functional communication bug is detected, a novel recovery algorithm reconstructs the data that was in flight at the time of the error occurrence, ensuring that it reaches the intended destination ...
The main NoC routers are based on the input-queued VC router of [10] , with 5 ports, 4 pipeline stages, 2 virtual channels, and 8 flit buffers. ...
Indeed, during recovery only one router in the primary network is active at a time, eliminating complex interactions and concurrent communication in the network. ...
doi:10.1109/iccd.2011.6081423
dblp:conf/iccd/Abdel-KhalekPDB11
fatcat:2ta4qnkbazh4hncgkrty7hbhha
Creating Repeatable Computer Science and Networking Experiments on Shared, Public Testbeds
2015
ACM SIGOPS Operating Systems Review
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Second, we generate a failure by bringing down a virtual link or a virtual router and recovering the failure after some time. ...
But the case study was done as part of a larger experiment to evaluate a selection algorithm to replace failed virtual routers in virtual networks. ...
doi:10.1145/2723872.2723884
fatcat:iysh4xljivgmvhm4iw3amtytca
A clustering-based scheme for concurrent trace in debugging NoC-based multicore systems
2012
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)
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In the proposed scheme, a unified communication framework eliminates the requirement for interconnection fabric which is only used during debugging. ...
Introduction In the design flow of integrated circuits (ICs), pre-silicon verification techniques, such as simulation or formal methods, aim to eliminating bug in a circuit before it is manufactured [ ...
Moreover, bugs are usually not predictable in multicore systems, whereas scan-based technology cannot deal with the un-reproducible bugs. ...
doi:10.1109/date.2012.6176427
dblp:conf/date/GaoWHZL12
fatcat:zfzhnathgbbttjcj6sxkbs3bay
Correct by Construction Networks Using Stepwise Refinement
2017
Symposium on Networked Systems Design and Implementation
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Building software-defined network controllers is an exercise in software development and, as such, likely to introduce bugs. ...
Our performance evaluation demonstrates that Cocoon is not only faster than existing verification tools but can also find many bugs statically before the network design has been fully specified. ...
In order to eliminate inconsistent definitions, Cocoon relies on assumptions. ...
dblp:conf/nsdi/RyzhykBCJSTV17
fatcat:7hu2shh4p5cqhl6brbodn2tvba
DEFINED: Deterministic Execution for Interactive Control-Plane Debugging
2013
USENIX Annual Technical Conference
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We demonstrate our system's advantages by reproducing discovery of known ordering and timing bugs in popular software routing platforms, XORP and Quagga. ...
As illustrated in Figure 5 , a router R 1 connects to two other routers R 2 and R 3 . ...
However, because internal nondeterminism is recorded only at border routers, the set of paths can still reach router R3 in a nondeterministic fashion. ...
dblp:conf/usenix/LinJCM13
fatcat:lqrknnvevrgyvgg3srhxxovvsq
Dataplane equivalence and its applications
2019
Symposium on Networked Systems Design and Implementation
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Our evaluation highlights that equivalence is an easy way to find bugs, scales well to relatively large programs and uncovers subtle issues otherwise difficult to find. ...
We use netdiff to find new bugs in Openstack Neutron, to test the differences between related P4 programs and to check the equivalence of FIB updates in a production network. ...
Tenant A creates a private virtual network and connects it to a public network via a virtual router, configuring source NAT on the external gateway of the router. ...
dblp:conf/nsdi/DumitrescuSPNR19
fatcat:yqnxrdyeojdhfjq6fhhggib3rm
Fast scalable FPGA-based Network-on-Chip simulation models
2011
Ninth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMPCODE2011)
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of magnitude speedup, depending on the network and router configuration. ...
For larger networks, where a direct-mapped approach is not feasible due to FPGA resource limitations, a virtualized time-multiplexed approach was used. ...
potential bugs. ...
doi:10.1109/memcod.2011.5970513
dblp:conf/memocode/Papamichael11
fatcat:j4cpckjovjf6tgkerjplpmkhtq
Advanced Network Simulation under User-Mode Linux
2005
DFN Tagungen
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E. g. when a user of the OpenSource Linux strongSwan VPN software reported an IPsec re-keying error occurring in conjunction with a NAT router, this rare problem could be reproduced in a virtual UML test ...
setup within two hours of simulation and a bug fix was found, tested and released on the same day. ...
This also provides a noticeable speedup by eliminating the signal delivery that used to happen for every UML system call. ...
dblp:conf/dfn/SteffenMR05
fatcat:ybd6v47wdzcf3jh4jl6bo6wira
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