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Virtual FPGAs: Some steps behind the physical barriers
[chapter]
1998
Lecture Notes in Computer Science
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This paper introduces and discusses the concept of Virtual FPGA as an extension of the physical FPGA device: applications have a virtual view of the FPGA that is then mapped on the available physical device ...
The physical dimensions of FPGAs (pinout and gate count) limit the complexity of circuits that can be implemented. ...
However, some physical limitations exist in the use of FPGAs. ...
doi:10.1007/3-540-64359-1_665
fatcat:oe754ymngzhyzmh2hpd4y3dovu
From OO to FPGA
2010
SIGPLAN notices
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Open until now is the problem of compiling an object-oriented language to an FPGA in a way that harnesses this potential for huge energy savings. ...
Ideally, software engineers can more readily take advantage of the benefits FPGAs offer by being able to program them using their existing skills, a common one being object-oriented programming. ...
The second author thanks David Bacon for many conversations about compiling OO to FPGA. ...
doi:10.1145/1932682.1869470
fatcat:qmk42gfebfftnpouwmcnibwkli
From OO to FPGA
2010
Proceedings of the ACM international conference on Object oriented programming systems languages and applications - OOPSLA '10
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Open until now is the problem of compiling an object-oriented language to an FPGA in a way that harnesses this potential for huge energy savings. ...
Ideally, software engineers can more readily take advantage of the benefits FPGAs offer by being able to program them using their existing skills, a common one being object-oriented programming. ...
The second author thanks David Bacon for many conversations about compiling OO to FPGA. ...
doi:10.1145/1869459.1869470
dblp:conf/oopsla/KouP10
fatcat:7kzlp3qsvfeajcrfc4ba3hv4iq
FPGA-based Digital Quantum Coprocessor
2018
Advances in Cyber-Physical Systems
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Message Authentication Code: A short code that is computed on some information using a key. The code can be used to check the integrity and authenticity of the information. ...
Quantum Algorithm: A step-by-step procedure that could be run on a working quantum computer. Quantum Computing: A computing device based on Qubits that can run quantum algorithms. ...
But physics presents a natural barrier in that once technology has shrunk a transistor to the size of a single atom there are no more improvements to be made to transistor size. ...
doi:10.23939/acps2018.02.067
fatcat:7txboogyr5f5vgc5c5zzbovv34
JackHammer: Efficient Rowhammer on Heterogeneous FPGA-CPU Platforms
[article]
2020
arXiv
pre-print
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platform, and the Arria 10 GX PAC expansion card which connects the FPGA to the CPU via the PCIe interface. ...
In some scenarios our JackHammer attack produces faulty signatures more than three times more often and almost three times faster than a conventional CPU rowhammer attack. ...
Daniel Moghimi was supported by the National Science Foundation under grant no. CNS-1814406. This work was partially supported by the German Research Foundation (DFG) project number 427774779. ...
arXiv:1912.11523v3
fatcat:s4mm6dydlzfkvh4r3zuq4uyvca
Graph Processing on FPGAs: Taxonomy, Survey, Challenges
[article]
2019
arXiv
pre-print
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Finally, we discuss research and engineering challenges to outline the future of graph computations on FPGAs. ...
This is reflected by the recent interest in developing various graph algorithms and graph processing frameworks on FPGAs. ...
Finally, a barrier synchronization guarantees that the next super-step only begins after all local computations in the current super-step are finished and all messages in this super-step are exchanged. ...
arXiv:1903.06697v3
fatcat:f5usapd45jgqpf7ynlz4w6e4si
Transparent Live Code Offloading on FPGA
[article]
2016
arXiv
pre-print
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new bit-stream to the FPGA each time a change is made. ...
Despite the improvements made by High-Level Synthesis (HLS), which removed the language and paradigm barriers that prevented many computer scientists from working with them, producing a new design typically ...
HLS [7, 8] partially mitigates these problems by removing the language barrier. ...
arXiv:1609.00130v1
fatcat:axxmo35bznffze52h3sgrtbnv4
FPGA-based accelerator development for non-engineers
2014
2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)
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However, domain experts, who are the brains behind this processing, typically lack the skills required to build FPGA-based hardware accelerators ideal for their applications, as traditional development ...
The efficacy of these flows in extending FPGA-based acceleration to non-engineers in the life sciences was informally tested at two separate instances of an NSF-funded summer workshop, organized and hosted ...
FPGAs can be configured at a fine level of granularity to execute virtually any hardware description. ...
doi:10.1109/reconfig.2014.7032522
dblp:conf/reconfig/UlianaAK14
fatcat:s6krmx2zerbffnpagsanagvjwy
Scalable and deterministic timing-driven parallel placement for FPGAs
2011
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays - FPGA '11
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Finally, it is shown that the amount of degradation in the parallel placer is independent of the number of threads used. ii ...
Specifically, at the point where the parallel placer begins to dominate over the serial placer, the post-routing minimum channel width, wirelength and critical-path delay degrades 13%, 10% and 7% respectively ...
to form each cluster as shown in Figure 2
Placement The placement step involves assigning each CLB in the circuit to a unique physical location on the FPGA chip, as shown in Figure 2 Figure 2 ...
doi:10.1145/1950413.1950445
dblp:conf/fpga/WangL11
fatcat:2xpnc3uhebclvftblpwskizlru
JackHammer: Efficient Rowhammer on Heterogeneous FPGA-CPU Platforms
2020
Transactions on Cryptographic Hardware and Embedded Systems
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platform, and the Arria 10 GX PAC expansion card which connects the FPGA to the CPU via the PCIe interface. ...
We demonstrate JackHammer, a novel, efficient, and stealthy Rowhammer from the FPGA to the host's main memory. ...
physical addresses in the virtual machine (what Intel calls I/O Virtual Addresses or IOVA) to physical addresses in the host. ...
doi:10.13154/tches.v2020.i3.169-195
dblp:journals/tches/WeissmanTMCES20
fatcat:scv3i3zbwfgcrd34dtqmqpbwz4
GraVF-M: Graph Processing System Generation for Multi-FPGA Platforms
[article]
2019
arXiv
pre-print
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Based on a lightweight description of the algorithm kernel, the framework automatically generates optimized RTL code for the whole multi-FPGA design. ...
In this work, we present GraVF-M, a framework designed to ease the implementation of FPGA-based graph processing accelerators for multi-FPGA platforms with distributed memory. ...
For be er performance, the network should o er separate (physical or virtual) channels for messages of di erent supersteps. ...
arXiv:1910.07408v1
fatcat:rpeekxca4nh6padscqwyt7zfza
Parallel Programming for FPGAs
[article]
2018
arXiv
pre-print
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A knowledge of the RTL-based FPGA design flow is helpful, although not required. ...
This book focuses on the use of algorithmic high-level synthesis (HLS) to build application-specific FPGA systems. ...
The first step in this process is understanding the basic concepts behind the computation of the FIR filter. ...
arXiv:1805.03648v1
fatcat:l2dxkvqcrbe73cpi7yupi7kyk4
Electronic- and Mobile-Learning in Electronics Courses Focused on FPGA
[chapter]
2012
E-Learning - Long-Distance and Lifelong Perspectives
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., 1991) , where teaching is provided through the development of projects that also involves the learners' performance and application of gained theoretical knowledge. ...
Thus, laboratory activity related to on-line teaching applied to scientific domains and remote control of instrumentation and the execution of real experiments via Internet have been becoming topics of ...
As E-learning and M-learning remove the physical, geographical and cultural barriers to the education and enable the learners to choose their own learning path and time, they are suitable to fulfil the ...
doi:10.5772/29911
fatcat:h4cuqhqb3nc4nbuxf3znvkzsym
OpenCL-based FPGA accelerator for disparity map generation with stereoscopic event cameras
[article]
2019
arXiv
pre-print
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In this work we present some experiments to create FPGA accelerators for a well-known vision algorithm using event-based cameras. ...
We present a stereo matching algorithm to create a stream of disparity events disparity map and implement several accelerators using the Intel FPGA OpenCL tool-chain. ...
ACKNOWLEDGMENTS This project was funded by the Spanish Ministry of Science, Innovation and Universities under the project TEC2014-59679-C2-2-R. ...
arXiv:1903.03509v1
fatcat:ham7gxc3trdlhm6x6ggesu2zna
Virtual radio: a framework for configurable radio networks
2008
Proceedings of the 4th International ICST Conference on Wireless Internet
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In this paper we describe the background to network virtualization and extend this concept into the wireless domain, which we denote as radio virtualization. ...
With radio virtualization different virtual radio networks can operate on top of a common shared infrastructure and share the same radio resources. ...
virtual network operator (Fig. 2 steps q-r) . ...
doi:10.4108/icst.wicon2008.4925
dblp:conf/wicon/SachsB08
fatcat:w73mgbkka5dj3o77ode7npdwla
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