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SRAM-Based FPGA Systems for Safety-Critical Applications: A Survey on Design Standards and Proposed Methodologies
2015
Journal of Computer Science and Technology
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Only a small number of standards for the design of safety-critical systems give guidelines and recommendations that take the peculiarities of the FPGA technology into consideration. ...
The main contribution of this paper is an overview of the existing design standards that regulate the design and verification of FPGA-based systems in safety-critical application fields. ...
Further, FPGA devices based on SRAM are the most susceptible to the adverse effects of radiations. ...
doi:10.1007/s11390-015-1530-5
fatcat:uq6yhul4cffnvgsjow7ccqvjgm
FPGA Architecture: Survey and Challenges
2007
Foundations and Trends® in Electronic Design Automation
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FPGA architecture has a dramatic effect on the quality of the final device's speed performance, area efficiency, and power consumption. ...
This survey focuses primarily on static memory-based FPGAs but, in this section, all these modern programming technologies will be reviewed to provide a more complete understanding of the advantages and ...
This survey has explored many issues in the complex and rapidly evolving world of pre-fabricated FPGA architectures. ...
doi:10.1561/1000000005
fatcat:ebex55milfgczim2i4wi2apbqy
Robust Convolutional Neural Networks in SRAM-based FPGAs: a Case Study in Image Classification
2021
Journal of Integrated Circuits and Systems
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The Caffe and Ristretto frameworks were used for CNN training and fine-tuning while the ZynqNet inference engine was adopted as hardware implementation on a Xilinx 28 nm SRAM-based FPGA. ...
This work discusses the main aspects of vulnerability and degradation of accuracy of an image classification engine implemented into SRAM-based FPGAs under faults. ...
de Desenvolvimento Científico e Tecnológico (CNPq); and Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP). ...
doi:10.29292/jics.v16i2.504
fatcat:4sfplv5g2fgbljzgtl64gkhode
Co-evolutionary Approach to Reduce Soft Error Rate of Implemented Circuits on SRAM_based FPGA
2018
International Journal of Computer Applications
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In this paper, we have developed a coevolutionary method to reduce the effect of soft error on the implemented circuit on FPGA. ...
Soft errors such as Single Event Upset (SEU) have great effect on performance degradation of circuits implemented on SRAM_based FPGA. ...
Soft Error Rate Estimation Soft errors such as SEU have great effect on FPGA memory elements in aerospace applications. ...
doi:10.5120/ijca2018917136
fatcat:w64tekvzcbe5hfm6ouwnex6u7m
Design Techniques for Xilinx Virtex FPGA Configuration Memory Scrubbers
2013
IEEE Transactions on Nuclear Science
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SRAM-based FPGAs are in-field reconfigurable an unlimited number of times. ...
This paper classifies and presents current and novel design methodologies and architectures for SRAM-based FPGAs, and in particular for Xilinx Virtex-4QV/5QV, configuration memory scrubbers. ...
In particular, mitigation techniques for the FPGA configuration layer are addressed in this paper. Scrubbing is an effective error mitigation technique for configuration memory in SRAM-based FPGAs. ...
doi:10.1109/tns.2012.2231881
fatcat:y34el2up7nhvzbrhecksrkogri
Optimally Fortifying Logic Reliability through Criticality Ranking
2015
Electronics
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The key idea is to prolong the lifetime of FPGA-mapped designs by strategically elevating the V DD values of some LUTs based on their modular criticality values. ...
Finally, we analytically prove, for the first time, that the optimal way to improve the overall reliability of a whole FPGA device is to fortify individual LUTs according to their modular criticality. ...
Conflicts of Interest The authors declare no conflicts of interest. ...
doi:10.3390/electronics4010150
fatcat:mal7hmtlobfkvkk7xqh2ecerqi
A Survey of fault models and fault tolerance methods for 2D bus-based multi-core systems and TSV based 3D NOC many-core systems
[article]
2022
arXiv
pre-print
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We examine the state of art fault mitigation techniques at the logical layer for digital CMOS based design and SRAM based FPGA. CMOS SRAM structure is the same for both digital CMOS and FPGA. ...
The article presents a congregation of concepts illustrated one after the other for a better understanding of damages caused by radiation, relevant fault models, and effects of faults. ...
Boolean logic Failure Rate Estimation in Digital CMOS vs SRAM based FPGA: -The masking effects makes Digital CMOS circuits less vulnerable as compared to SRAM based FPGA. ...
arXiv:2203.07830v1
fatcat:dsbx3o4v3femhi5d6kfrurzuoi
Fault tolerant electronic system design
2017
2017 IEEE International Test Conference (ITC)
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As the CFC module focuses only on the CFEs, a hybrid technique was proposed with dual control flow monitoring to detect soft errors, together with a software-based technique targeting on Data Errors. ...
Other phenomena (e.g., aging and wear-out effects) also have negative impacts on reliability of modern circuits. ...
Matteo Sonza Reorda for providing ...
doi:10.1109/test.2017.8242080
dblp:conf/itc/DuS17
fatcat:fyonsldknjcutb5p2hiq6brcd4
On line self recovery of embedded multi-processor SOC on FPGA using dynamic partial reconfiguration
2012
Information Technology and Control
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An error-recovery method for embedded multi-processor systems on SRAM-based FPGAs is proposed. ...
This method is effective against soft-errors in the configuration memory, such as the errors caused by hIgh energy radiation also known as Single Event Upsets. ...
Introduction Some SEU mitigation techniques use time redundancy but they are effective only against SRAM-based FPGA devices are steadily becoming transient faults. ...
doi:10.5755/j01.itc.41.2.896
fatcat:p3svd6nd5zelhnrkzbw2sjdo4m
Analysis and test of the effects of single event upsets affecting the configuration memory of SRAM-based FPGAs
2014
2014 International Test Conference
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These faults have particularly adverse effects on SRAM-based FPGA systems because not only can they temporarily affect the behaviour of the system by changing the contents of flip-flops or memories, but ...
Memory of SRAM-based FPGAs, a static analysis tool for the identification of the untestable SEUs and for the automatic generation of test patterns for in-service testing of the 100% of the testable SEUs ...
In the remainder of this section we focus on the techniques and tools specifically focused on the analysis of the effects of SEUs in SRAM-based FPGAs that can be found in the literature. ...
doi:10.1109/test.2014.7035366
dblp:conf/itc/Cassano14
fatcat:ykg7k6finnhwpk7j6zsbtlwfkq
Availability analysis for satellite data processing systems based on SRAM FPGAs
2016
IEEE Transactions on Aerospace and Electronic Systems
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This paper presents a novel methodology, which allows a systematic availability analysis of satellite payload data processing systems implemented on SRAM-based FPGAs. ...
With the proposed Block RAM profiling tool it is possible to determine a realistic reliability figure that is eventually required for the accurate estimation of the system availability. ...
We wish to thank the reviewers for their constructive comments and suggestions for improvement. ...
doi:10.1109/taes.2016.140914
fatcat:i2ij7uhzybbvxeex4hlbpvk6ey
Validation of FDIR Strategy for Spaceborne SRAM-Based FPGAs Using Proton Radiation Testing
2015
2015 15th European Conference on Radiation and Its Effects on Components and Systems (RADECS)
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This paper presents a novel stream processor architecture for SRAM-based FPGAs that is specifically targeted at payload data processing and which employs innovative Fault Detection, Isolation and Recovery ...
By means of an accelerated proton irradiation test campaign, both the FDIR framework and the availability analysis method are validated. ...
ACKNOWLEDGMENTS Sponsorship from ESA under the NPI Programme, Airbus Defence and Space, UK and the University of Leicester is gratefully acknowledged. ...
doi:10.1109/radecs.2015.7365694
fatcat:fozhsgv2ebeb5cyqhsx74fouxa
Mitigation of Radiation Effects in SRAM-Based FPGAs for Space Applications
2015
ACM Computing Surveys
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ACKNOWLEDGMENTS Sponsorship from ESA under the NPI Programme, Airbus Defence and Space, UK and the University of Leicester is gratefully acknowledged. ...
Therefore, in the following the focus is on these devices.
Radiation Effects in SRAM-based FPGAs for Space 2.2.1. Sources of Radiation Effects. ...
A comprehensive coverage of all aspects of radiation effects design mitigation for SRAM-based FPGAs on board spacecraft is given. ...
doi:10.1145/2671181
fatcat:hj2zikuhfnh4xn3zvjnt3ihmdu
A Fault-Tolerant Time-Predictable Processor
2019
2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)
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In this paper, a triple-core lock-step processor for radiation-induced soft-errors mitigation is presented that aims to reduce the probability of a processor failure due to softerrors. ...
However, a high integration level within an FPGA causes high sensitivity to ionising radiation-induced errors, requiring mitigation for single event effects to ensure reliable operation. ...
Acknowledgement The work presented in this paper was partially funded by the Danish Council for Independent Research | Technology and Production Sciences under the project PREDICT 1 (no. 4184-00127A). ...
doi:10.1109/norchip.2019.8906947
dblp:conf/norchip/GkiokasS19
fatcat:iwhembkaanbvldz4zubz2kx5au
Space-Based FPGA Radio Receiver Design, Debug, and Development of a Radiation-Tolerant Computing System
2010
International Journal of Reconfigurable Computing
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Using two Xilinx Virtex 4 FPGAs, we have achieved 1 TeraOps/second signal processing on a 1920 Megabit/second datastream. ...
This paper will discuss the design of the payload, making electronics survivable in the radiation of space, and techniques for debug. ...
The authors also recognize the contributions of our commercial partners, Xilinx, Lockheed-Martin, BAE Systems, Linear Technology, and Texas Instruments. This document is released under LA-UR 10-06455. ...
doi:10.1155/2010/546217
fatcat:t5xbmrjourhz3ntx4le2pvvtei
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