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Simulation based architectural power estimation for PLA-based controllers
Proceedings of 1996 International Symposium on Low Power Electronics and Design
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We present an architectural power simulation technique for PLA-based c ontrollers. ...
For a given input sequence, the modied vhdl description is simulated to estimate the total power consumption. ...
estimation technique for pla-based controllers. ...
doi:10.1109/lpe.1996.547492
dblp:conf/islped/KatkooriV96
fatcat:bvf5el46w5g7lco6ctnr7bd7ly
Activity-sensitive architectural power analysis for the control path
1995
Proceedings of the 1995 international symposium on Low power design - ISLPED '95
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This paper focuses on the control path, describing a novel power analysis strategy known as the Activity-Based Control (ABC) model. ...
In a previous publication, we introduced architecture-level power analysis techniques for datapath and memory modeling. ...
Acknowledgments The authors would like to thank Arthur Abnous for his significant contributions to the SPA project -in particular, his implementation of the ADL and CDL parsers and of the VHDL code generator ...
doi:10.1145/224081.224098
dblp:conf/islped/LandmanR95
fatcat:hiwx7226dfcrhcdzqvhrcf5ruq
Architectural Power Estimation Based on Behavior Level Profiling
1998
VLSI design (Print)
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the total switched capacitance of each component.Detailed power estimation procedures for the three different parts of RTL designs, namely, data path, controller and interconnect are presented. ...
Experimental results obtained from a variety of designs show that the power estimates are within 3%–10% of the actual power measured by simulating the transistor level designs extracted from mask layouts ...
Power Estimation in Controller The controller is a finite state machine implemented as a PLA. ...
doi:10.1155/1998/93106
fatcat:dbj3fnjmjncxvh4uli5dm56niu
Bipartitioning and encoding in low-power pipelined circuits
2005
ACM Transactions on Design Automation of Electronic Systems
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In this article, we present a bipartition dual-encoding architecture for low-power pipelined circuits. ...
The transistor-level simulation results show that bipartition dual-encoding can effectively reduce power by 72.7% for the pipeline registers and 27.1% for the total power consumption on average. ...
To validate the results, we employ the accurate transistor-level power estimator EPIC PowerMill 1 to estimate power dissipation. The rest of the article is organized as follows. ...
doi:10.1145/1044111.1044114
fatcat:rwnrlrxunbgjrdxinniybh5atq
Programmable logic circuits based on ambipolar CNFET
2008
Proceedings of the 45th annual conference on Design automation - DAC '08
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The simulations show an area saving up to ∼ 21% and decrease of the delay in PLA-based FPGA by 50%. ...
We also show that this architecture is suitable for highperformance design tools and defect-tolerance approaches. ...
This powerful feature potentially reduces the size of the PLA even if the size of the basic cell is large. This area was estimated from the scaling rules suggested in [5] for CNFET. ...
doi:10.1145/1391469.1391556
dblp:conf/dac/JamaaALM08
fatcat:p7d6qetyazfy3e4hroy5zruyc4
High-throughput VLSI Implementations of Iterative Decoders and Related Code Construction Problems
2007
Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology
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The operating power, delay and chip-size of the circuits are estimated, indicating that the proposed method significantly outperforms presently used standard-cell based architectures. ...
We describe an efficient, fully-parallel Network of Programmable Logic Array (NPLA)-based realization of iterative decoders for structured LDPC codes. ...
Acknowledgements The authors wish to thank Thorsten Hehn for his help with the PEG algorithm and PEG code simulations and for helpful discussions. ...
doi:10.1007/s11265-007-0054-9
fatcat:qcrhzbv7y5fftoixuwllfj6dim
High-throughput VLSI implementations of iterative decoders and related code construction problems
2004
IEEE Global Telecommunications Conference, 2004. GLOBECOM '04.
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The operating power, delay and chip-size of the circuits are estimated, indicating that the proposed method significantly outperforms presently used standard-cell based architectures. ...
We describe an efficient, fully-parallel Network of Programmable Logic Array (NPLA)-based realization of iterative decoders for structured LDPC codes. ...
Acknowledgements The authors wish to thank Thorsten Hehn for his help with the PEG algorithm and PEG code simulations and for helpful discussions. ...
doi:10.1109/glocom.2004.1377970
dblp:conf/globecom/NagarajanJKM04
fatcat:z6z7otvat5hcvnoslxvhd7qrdu
CARAM: A Content-Aware Hybrid PCM/DRAM Main Memory System Framework
[article]
2020
arXiv
pre-print
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The emergence of Phase-Change Memory (PCM) provides opportunities for directly connecting persistent memory to main memory bus. ...
A naturally inspired design is the hybrid memory architecture that fuses DRAM and PCM, so as to exploit the positive aspects of both types of memory. ...
Yang Wu for their help on the initial design of the system. ...
arXiv:2007.13661v1
fatcat:pkwbsjdt4nfztaoaatofocrb6a
Towards a framework for designing applications onto hybrid nano/CMOS fabrics
2009
Microelectronics Journal
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Our proposal is based on a variety of models that capture as well as isolate the differences between these fabrics. ...
The design of CAD tools for nanofabrics involves new challenges not encountered with conventional design flow used for CMOS technology. ...
The fault model of the fabric is essentially used for estimating the yield of the circuit based on its architectural description. ...
doi:10.1016/j.mejo.2008.07.072
fatcat:te4h6zgiincqfnngggutvziuia
High-Level Energy Estimation for ARM-Based SOCs
[chapter]
2004
Lecture Notes in Computer Science
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Addressing this issue, we developed an energy-aware architectural design exploration and analysis tool for ARM based system-on-chip designs. ...
The tool integrates the behavior and energy models of several user-defined, custom processing units as an extension to the cycle-accurate instruction-level simulator for the ARM low-power processor family ...
A separate model is introduced to handle power estimation for control logic and signals. This model is called the Activity-Based Control (ABC) model. ...
doi:10.1007/978-3-540-27776-7_18
fatcat:iuwrikedffa3tcrqpjhrcnl3k4
PLAs in Quantum-Dot Cellular Automata
2008
IEEE transactions on nanotechnology
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Specifically, we present a novel, QCA-based, Programmable Logic Array (PLA) structure. ...
Our PLA is capable of providing defect tolerance at both the device and architectural level, and limits the amount of determinism required in any fabrication process. ...
While a detailed discussion of fault models and yield estimates for our PLA structure is beyond the scope of this paper, we do briefly describe a set of MAQUINAS simulations to discuss how interconnect ...
doi:10.1109/tnano.2007.915022
fatcat:6ggu4ji2uvcohieobqz3y3s3my
Learning to Engage with Interactive Systems: A Field Study on Deep Reinforcement Learning in a Public Museum
[article]
2020
arXiv
pre-print
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Although many advances have been made for one-to-one interactions in well controlled settings, future physical agents should be capable of interacting with humans in natural settings, including group interaction ...
In this paper, we propose an approach for estimating engagement during group interaction by simultaneously taking into account active and passive interaction, i.e. occupancy, and use the measure as the ...
This work was supported by the Living Architecture Systems Group, funded by the Social Sciences and Humanities Research Council of Canada. ...
arXiv:1904.06764v2
fatcat:34vsnavn6jhbhis4sid2s4r7ay
An SDN Control Plane for Multiband Networks Exploiting a PLI-aware Routing Engine
2022
Zenodo
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We report the design of a TAPI SDN control plane for multi-band networks with externalized PLI-aware RMSA. ...
We detail the architecture, data model extensions, algorithms and the implementation and validation in an emulated BT 22-ROADM network. © 2022 The Author(s) ...
As such, the P ch,opt is re-estimated based on the approach of [4] whenever a quanta of 5 channels is introduced in the network. ...
doi:10.5281/zenodo.7257575
fatcat:xu7b5i4b5vgbratanhhiq4znc4
An SDN Control Plane for Multiband Networks Exploiting a PLI-aware Routing Engine
2022
Zenodo
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We report the design of a TAPI SDN control plane for multi-band networks with externalized PLI-aware RMSA. ...
We detail the architecture, data model extensions, algorithms and the implementation and validation in an emulated BT 22-ROADM network. © Optica Publishing Group 2022, © 2022 The Author(s) ...
As such, the P ch,opt is re-estimated based on the approach of [4] whenever a quanta of 5 channels is introduced in the network. ...
doi:10.5281/zenodo.7260206
fatcat:us56b7vmwzfunilo2nyvd4hmv4
Serpens: A Highly Compliant Low-Cost ROS-Based Snake Robot with Series Elastic Actuators, Stereoscopic Vision and a Screw-Less Assembly Mechanism
2019
Applied Sciences
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The software architecture is based on the Robot Operating System (ROS). ...
The concept of modularity is also applied to the system architecture on both the software and hardware sides. Each module is independent, being controlled by a self-reliant controller board. ...
The OpenCM 9.04 micro-controller is connected to and powered by an external computer running the proposed ROS-based architecture. The communication is achieved by using the rosserial package [36] . ...
doi:10.3390/app9030396
fatcat:p4q7hnav35fmlifdw7w2u4fwcm
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