A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
Filters
An integrated partitioning and synthesis system for dynamically reconfigurable Multi-FPGA architectures
[chapter]
1998
Lecture Notes in Computer Science
Preserved Fulltext
A distinguishing feature of the sparcs system is the tight i n tegration of the partitioning and synthesis tools to accurately predict and control design performance and resource utilizations. ...
This paper presents an integrated design system called sparcs Synthesis and Partitioning for Adaptive Recon gurable Computing Systems for automatically partitioning and synthesizing designs for recongurable ...
Summary We presented an integrated design environment for automatically partitioning and synthesizing behavioral speci cations onto multi-fpga based recon gurable computers. ...
doi:10.1007/3-540-64359-1_669
fatcat:zslppqtsk5bxrgapwyix4yfoxq
Multilevel Granularity Parallelism Synthesis on FPGAs
2011
2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2013; you can also visit the original URL.
The file type is application/pdf.
However implementation and performance evaluation of the HLS-generated RTL, involves lengthy logic synthesis and physical design flows. ...
We leverage resource and clock period models to estimate the impact of multi-granularity parallelism extraction on execution cycles and frequency. ...
Research of Singapore. ...
doi:10.1109/fccm.2011.29
dblp:conf/fccm/PapakonstantinouLSGCHC11
fatcat:krlcxo36ebeojfy7neqtu642kq
Golden Gate: Bridging The Resource-Efficiency Gap Between ASICs and FPGA Prototypes
2019
2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2021; you can also visit the original URL.
The file type is application/pdf.
We present Golden Gate, an FPGA-based simulation tool that decouples the timing of an FPGA host platform from that of the target RTL design. ...
In contrast to previous work in static time-multiplexing of FPGA resources, Golden Gate employs the Latency-Insensitive Bounded Dataflow Network (LI-BDN) formalism to decompose the simulator into subcomponents ...
We also wish to thank Pramod Subramanyan for his valuable insights on LIME and Murali Vijayaraghavan for his correspondence on LI-BDNs. ...
doi:10.1109/iccad45719.2019.8942087
dblp:conf/iccad/MagyarBKSBA19
fatcat:4xjzrmr245bjtj5hcbexq2fhue
Design and implementation of a multi-channel space-borne SAR imaging system on Vivado HLS
2018
IEICE Electronics Express
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2018; you can also visit the original URL.
The file type is application/pdf.
The modules designed on HLS are optimized and packaged as IP blocks for FPGA implementation of the imaging system. ...
In order to reduce FPGA design cost, a high-level synthesis tool Xilinx Vivado HLS is applied to design and implement the SAR imaging system. ...
C testbench
Source code
(C/C++/SystemC)
C simulation
C synthesis
Constraints/
Directives
RTL code
(VHDL/
Verilog)
RTL Simulation
RTL
Adapter
Packaged IP
Vivado HLS
Vivado Design ...
doi:10.1587/elex.15.20180254
fatcat:3wpwxqlqmzeqrjgtswjx3kti5m
On the RTL Implementation of FINN Matrix Vector Compute Unit
[article]
2022
arXiv
pre-print
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2022; you can also visit the original URL.
The file type is application/pdf.
Other Versions
Overall, since HLS frameworks code-generate the hardware design, the benefits of the ease in the design entry is less important as compared to synthesis time reduction togther with resource benefits, this ...
To reduce the barrier for software engineers and data scientists to adopt FPGAs, C++- and OpenCL-based design entries with high-level synthesis (HLS) have been introduced. ...
Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author and do not necessarily reflect the views of the Science Foundation Ireland and European Union's ...
arXiv:2201.11409v2
fatcat:3ml3qtizijel5mkbxaothn4ara
Automatic translation of software binaries onto FPGAs
2004
Proceedings of the 41st annual conference on Design automation - DAC '04
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2012; you can also visit the original URL.
The file type is application/pdf.
Results show performance gains of 3-20X in the FPGA designs over that of the DSP processors in terms of reductions of execution cycles. ...
The introduction of advanced FPGA architectures, with built-in DSP support, has given DSP designers a new hardware alternative. ...
Transfer Level (RTL) VHDL or Verilog code for FPGAs. ...
doi:10.1145/996566.996678
dblp:conf/dac/MittalZTB04
fatcat:2k2ys53y5fbplfqcdjlumthqx4
TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical Design
2023
ACM Transactions on Reconfigurable Technology and Systems
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2023; you can also visit the original URL.
The file type is application/pdf.
In our experiments with a total of 43 designs, we improve the average frequency from 147 MHz to 297 MHz (a 102% improvement) with no loss of throughput and a negligible change in resource utilization. ...
In addition, TAPA implements several optimization techniques specifically tailored for modern HBM-based FPGAs. ...
ACKNOWLEDGMENTS The authors acknowledge the valuable support of the Xilinx Adaptive Compute Clusters (XACC) Program. We thank Gurobi and GNU Parallel for their support to academia. ...
doi:10.1145/3609335
fatcat:xqznt2gg5baxbpv34doyydspre
Minimizing DSP block usage through multi-pumping
2015
2015 International Conference on Field Programmable Technology (FPT)
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
RELATED WORK A significant amount of research has been done on resource sharing at the RTL level as well as in high-level synthesis. ...
This is integrated in a high-level tool which takes datapath descriptions in C and generates synthesisable Verilog RTL with different levels of resource sharing. ...
doi:10.1109/fpt.2015.7393146
dblp:conf/fpt/RonakF15
fatcat:22mjytf53vgndcx5aqvrcfhwha
Improved resource sharing for FPGA DSP blocks
2016
2016 26th International Conference on Field Programmable Logic and Applications (FPL)
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2019; you can also visit the original URL.
The file type is application/pdf.
This is integrated in a high-level tool which takes datapath descriptions in C and generates synthesisable Verilog RTL with different levels of resource sharing. ...
Sharing multi-cycle hardware blocks like the DSP48E1 primitive in Xilinx FPGAs can result in significant resource savings, but complicates scheduling. ...
RELATED WORK A significant amount of research has been done on resource sharing at the RTL level as well as in high-level synthesis. ...
doi:10.1109/fpl.2016.7577373
dblp:conf/fpl/RonakF16
fatcat:y2i5qdl47bbkjfkoh3sgx6nfim
A reconfigurable signal processing IC with embedded FPGA and multi-port flash memory
2003
Proceedings of the 40th conference on Design automation - DAC '03
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
Code, data and FPGA bitstreams are stored in the embedded Flash memory and are independently accessible through 3 content-specific, 64-bit I/O ports with a peak read rate of 1.2GB/s. ...
A 1GOPS dynamically reconfigurable processing unit with embedded Flash memory and SRAM-based FPGA targets imagevoice processing and recognition applications. ...
The authors thank all the colleagues of NVM-DP Dept., A. Maurelli, F. Piazza and L. Fumagalli. ...
doi:10.1145/775832.776007
dblp:conf/dac/BorgattiCSFILMPPR03
fatcat:4m6go2krffe4tj5j2zg3eqm7kq
A reconfigurable signal processing IC with embedded FPGA and multi-port flash memory
2003
Proceedings of the 40th conference on Design automation - DAC '03
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
Code, data and FPGA bitstreams are stored in the embedded Flash memory and are independently accessible through 3 content-specific, 64-bit I/O ports with a peak read rate of 1.2GB/s. ...
A 1GOPS dynamically reconfigurable processing unit with embedded Flash memory and SRAM-based FPGA targets imagevoice processing and recognition applications. ...
The authors thank all the colleagues of NVM-DP Dept., A. Maurelli, F. Piazza and L. Fumagalli. ...
doi:10.1145/776004.776007
fatcat:kwkr5nmlrrc35ciztgfkj24x7q
Incremental compilation for parallel logic verification systems
2002
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2003; you can also visit the original URL.
The file type is application/pdf.
Important aspects of this work include the formulation and analysis of two incremental design mapping steps: the partitioning of newly added design logic onto multiple logic processors and the communication ...
It is shown that our incremental approach reduces verification compile time for modified designs by up to a factor of five versus complete design recompilation for benchmarks of over 100 000 gates. ...
Examples of design translation include RTL synthesis, technology mapping for FPGA-based logic emulators, and Boolean reduction for time-sequenced logic processors. ...
doi:10.1109/tvlsi.2002.801614
fatcat:r6l3cna55zbsvc2jcnrj7bhiju
Dovado: An Open-Source Design Space Exploration Framework
2021
2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2022; you can also visit the original URL.
The file type is application/pdf.
Hence, this work proposes Dovado, an open-source CAD tool for design space exploration (DSE) tailored for FPGAs-based designs. ...
Traditional hardware development exploits description languages such as VHDL and (System)Verilog to produce highly parametrizable RTL designs. ...
ACKNOWLEDGEMENTS The authors are grateful for precious feedbacks from anonymous reviewers and our colleagues M. Salaris, F. Peverelli, E. D'Arnese, E. Del Sozzo. ...
doi:10.1109/ipdpsw52791.2021.00027
fatcat:u2pcj5odijgmllcwfxewggpzey
TAPA: A Scalable Task-Parallel Dataflow Programming Framework for Modern FPGAs with Co-Optimization of HLS and Physical Design
[article]
2022
arXiv
pre-print
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2022; you can also visit the original URL.
The file type is application/pdf.
In our experiments with a total of 43 designs, we improve the average frequency from 147 MHz to 297 MHz (a 102% improvement) with no loss of throughput and a negligible change in resource utilization. ...
In addition, TAPA implements several optimization techniques specifically tailored for modern HBM-based FPGAs. ...
The authors acknowledge the valuable support of the Xilinx Adaptive Compute Clusters (XACC) Program. We thank Gurobi and GNU Parallel for their support to academia. ...
arXiv:2209.02663v1
fatcat:x6nwgcq6zrgwldhdmmx5yjgd2e
Run-time support for dynamically reconfigurable computing systems
2003
Journal of systems architecture
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
and even the lack of supporting operating systems for the existing optimally reconfigurable devices. ...
Many factors have been pointed out for further improvements so that the under laying technology can be rapidly boosted up so that to support the requirements of the emerging scientific applications. ...
multi-device ASIC design flow involving elements in response to the changing operating pin-constrained device partitioning like concepts [13]. conditions and data sets of the running application. ...
doi:10.1016/s1383-7621(03)00068-7
fatcat:weqgn7zw6ndcpggtkwcfcgtj44
« Previous
Showing results 1 — 15 out of 675 results