Reduce Register Files Leakage Through Discharging Cells.

When a register is dead, we discharge its cells to '0' to greatly reduce the leakage current from the read bitlines to the ground. Our design has no impact to critical register read access path. ... We propose a low-leakage register file cell design based on the observation that the physical registers in a superscalar processor have very short life cycles. ... There have been various techniques to reduce the leakage power of a register file. ...

doi:10.1109/iccd.2006.4380803 dblp:conf/iccd/JinWYZZ06 fatcat:szmwsf3cmrbwzhmu2pn7ymk3qi

Independently, turning off idle register file subbanks saves over 67% of leakage energy (57% total register file energy) with no loss in performance. ... In the register file, fine-grained read port deactivation saves nearly 50% of leakage energy and 22% of total energy. ... Dynamically deactivating idle registers reduces register file leakage energy by up to 67.1% and total register file energy by 57.1%. ...

doi:10.1145/545214.545231 fatcat:p7aivcpjkbelnmzn3del4rfnsy

Some of the superscalar processors, such as the Intel processor implement physical registers using the Reorder Buffer (ROB) slots. ... Many circuit and micro-architectural innovations have been proposed to reduce power in many individual processor units. ... Accordingly, by eliminating the leakage in memory cells, we can eliminate the bit line leakage. The ROB and register file utilization is relatively low. ...

doi:10.9790/4200-04113843 fatcat:dpqzzlznjvfmnnfvxkfj7t4g7i

Recent CMOS technology scaling has seriously eroded the bit-line noise immunity of register files due to the consequent increase in active bit-line leakage currents. ... To restore its noise immunity while maintaining performance, we propose and evaluate a 256×40-bit register file incorporating dual-V t bit-lines with a boosted gate overdrive voltage in 65 nm bulk CMOS ... However, lower V t causes transistor sub-threshold leakage currents to increase exponentially; and hence the bit-line active leakage currents of register files also increase exponentially and the noise ...

doi:10.5573/jsts.2009.9.3.148 fatcat:okagfj47eve2ppws5lj4hlujt4

The reduction in leakage is up to 33% for reorder buffer and 37% for integer and floating-point register files. ... The total energy-delay product is reduced, on average, by 15, 26, 20 and 17% for the reorder buffer, the integer register file, the floating-point register file and the instruction queue respectively. ... It should be noted that most of the leakage of bit lines is due to the leakage currents of memory cells, which flow through the two off pass transistor to the bit lines. ...

doi:10.1109/icsamos.2008.4664864 dblp:conf/samos/HomayounMGV08 fatcat:nszdilauifaqvh736emdrikd4q

files. ... This paper proposes such a centralized approach that attempts to simultaneously reduce power in processor units with highest dissipation: reorder buffer, instruction queue, load/store queue, and register ... It should be noted that most of the leakage of bit lines is due to the leakage currents of memory cells, which flow through the two off pass transistor to the bit lines. ...

doi:10.1109/tvlsi.2010.2064185 fatcat:precfxqwtra77kqgy2oh6maj6m

This paper details the design of a 64 × 32 bit 4-read 2write register file in TSMC 65 nm LP process. The register file avoids cell banking with pseudo-differential sensing scheme. ... Moreover, this approach enables a fully shareable and completely symmetry cell layout which shows competitive area results. ... Besides, for VDD = 1.2 V, T = 25 • C, the leakage current of the register file is 2.6 uA. Tab. I gives the comparison of this design with some previous work. ...

doi:10.1587/elex.9.1355 fatcat:draacuowtzhfffkwmwfidr7hcq

an exponential increase in subthreshold leakage. ... To keep dynamic power constant across process generations, traditional MOSFET scaling theory prescribes reducing supply and threshold voltages in proportion to device dimensions, a practice that induces ... Differential writes within the register file reduce write power during write backs. ...

doi:10.1145/1816038.1816012 fatcat:mywg5wkalfcdvp73cnaaolhxbe

an exponential increase in subthreshold leakage. ... To keep dynamic power constant across process generations, traditional MOSFET scaling theory prescribes reducing supply and threshold voltages in proportion to device dimensions, a practice that induces ... Differential writes within the register file reduce write power during write backs. ...

doi:10.1145/1815961.1816012 dblp:conf/isca/GuoIS10 fatcat:x25nvdcmjvfoth77qzaw65hpvq

As instructions pass through the pipeline, TM-RF places the bit-cells in different modes based on the register activity, thereby achieving significant power reduction. ... Index Terms-Leakage current, low power, bias temperature instability (NBTI/PBTI), process variation, register file (RF). 1063-8210 ... Because most of the leakage current of bit-lines flows from the bit-cells, reducing the leakage in bit-cells can eliminate the bit-line leakage [25] . ...

doi:10.1109/tvlsi.2014.2334136 fatcat:odbpvvtipjegheztiiewhx74ay

Leakage currents in on-chip SRAMs: caches, branch predictor, register files and TLBs, are major contributors to the energy dissipated by processors in deep sub-micron technologies. ... Previous work has addressed major sources of SRAM leakage in memory cells and bit-lines, making remaining SRAM components, in particular large drivers, the primary source of leakage. ... Jin et al. proposed a low-leakage register file cell design exploiting the observation that physical registers have short life cycles [33] . ...

doi:10.1145/1787275.1787339 dblp:conf/cf/HomayounSGVKD10 fatcat:c2rmsoklcnaorhg3tciru2wa2q

The keeper transistor is forced to be turned off adaptively to decrease the leakage current and the contention current to achieve high performance. ... The LBL in NCS contributes to the most power consumption of a large scale register files. In this state the evaluation node Q cannot be discharged to Gnd, so the node OUT is al ways low. ... Thus, some stored data in cell can be output through the GBL through the control of the decoder circuit. SIMULATION RESULTS With SMIC 65 nm [9] technology, 4 kinds of LBL are simulated. ...

doi:10.1109/icsict.2014.7021466 fatcat:7kwcgm4tdfch7c2zr6batxvr3i

Index Terms-Bitline active leakage, dc noise robustness, dual threshold voltage, pseudostatic, register files. ... This paper describes a 256-word 32-bit 4-read, 4-write ported register file for 6-GHz operation in 1.2-V 130-nm technology. ... Fig. 6 shows the register file bitcell, with symmetric loading of two read ports on each side of the storage cell for optimal cell write stability [6] . ...

doi:10.1109/4.997856 fatcat:ubdfkcosyjhqnijvf26qdnso3m

Wide fan-in dynamic multiplexers are one of the critical circuits of read-out paths in high-speed register files. ... Both improve noise tolerance, and both reduce the switching power by limiting the voltage swing on the large bitline capacitance through the introduction of dual dynamic nodes. ... Due to the stacking (self-reverse bias) effect, the leakage current through the nMOS access transistors connected to the read word lines is also reduced. ...

doi:10.1109/tcsi.2012.2220457 fatcat:twliqj3winhltpjsuqvnkk7czm

through the various new Technologies like increasing parallel operations, pipe line concepts [1] etc. ... Even though durable DC batteries are available in the market to operate the various electronic gadgets for more time, electronic designers are continuously concentrating more and more to reduce the power ... The output of accumulator goes to output buffer, ALU and register file. Register file: Eight locations are there for register file. Each location size is 8 bit length. ...

doi:10.35940/ijrte.a5927.0510121 fatcat:o3sp3ecgkbdwvpokmi3uvsnexa

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