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Logic Encryption for Resource Constrained Designs
2021
IEEE Access
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Logic Encryption is a hardware security technique that protects integrated circuit designs that are fabricated at untrusted pure play foundries from being pirated or maliciously modified. In the technique, logic gates are added to the design that are driven by an added key input bus, such that the correct behavior of the circuit is recovered with only the exact correct key input pattern. However, the power, performance, and area (PPA) cost of implementing logic encryption has often been ignored
doi:10.1109/access.2021.3059163
fatcat:t5acslbhvzemjmmpftyfzsmi54
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... in the literature in favor of increasing the level of security provided. This has proved to be a significant hurdle in transitioning the method to use in commercial-grade designs and a systematic methodology of constraining the cost of logic encryption is needed. In this paper, we propose a generalized Constraint-Directed Logic Encryption (CDLE) methodology. In CDLE, the potential design space of encrypted versions of a circuit is searched to apply logic encryption under PPA constraints. Two example CDLE methods are proposed. The first is a concurrent tree search method which uses commercial tools to sample designs for their PPA cost and determine the optimal encryption strategy. In this method, PPA cost is accurately analyzed at the cost of heavy runtime. The second is a machine learning approach which estimates the PPA cost to predict the optimal encryption strategy. The machine learning model developed in this work is limited, but the results are promising as a direction for study in logic encryption. Detailed experimental results evaluating both methods are presented. INDEX TERMS Hardware security, integrated circuits, logic encryption, cost metrics, logic synthesis, machine learning.
Temporal precondition verification of design transformations
[chapter]
1992
Lecture Notes in Computer Science
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Design transformations are ubiquitous in design derivation systems. Many such transformations have elaborate conditions of applicability known as preconditions. Usually, preconditions have both spatial and temporal components. The temporal (components of the) preconditions are usually specified by associating a dynamic interpretation with the design description at hand. Such dynamic interpretations have a semantic content which is based on interpreting the design description over the domain of
doi:10.1007/3-540-55179-4_13
fatcat:ehws5mvgejhb5nf4qeikobagne
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... atural numbers. Thus the problem of precondition verification is just as difficult as the problem of design verification itself. This paper is an informal exposition to the techniques we have used in verifying preconditions of the design transformations in a transformational exploration system for register-level hardware designs. These techniques are based on a purely syntactic interpretation of the design description and avoid the difficulties associated with the theorem proving techniques one could employ when a semantic interpretation is associated. While not as powerful as theorem proving methods, we found these techniques to be adequate for most cases of precondition verification of useful design transformations, at least within the design domain, namely register-level hardware, considered.
MAGELLAN
2001
Proceedings of the ninth international symposium on Hardware/software codesign - CODES '01
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An Integrated Online Scheduling and Placement Methodology
[chapter]
2004
Lecture Notes in Computer Science
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Dynamic task scheduling and online placement are two of the main responsibilities of an operating system for reconfigurable platforms. Since these operations are performed during run-time of the applications, these are overheads on the execution time. There is a need to find fast and efficient algorithms for task placement and scheduling. We propose an integrated online scheduling and placement methodology. We maintain empty area as a list of maximal empty rectangles which allows us to explore
doi:10.1007/978-3-540-30117-2_46
fatcat:466ga6j5n5gwpcvravlnvo55eq
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... olution space efficiently. We defer scheduling decisions until it is absolutely necessary to accommodate dynamically changing task priorities. We propose task queue management data-structures for in-order and out-of-order task scheduling strategies. One of our queuing strategies guarantees the shortest execution time for in-order task execution and the other strategy results in better FPGA area utilization for out-of-order task execution. We provide experimental evidence of improvement our methodology yields over the previous approaches.
Memory Synthesis for FPGA-Based Reconfigurable Computers
[chapter]
2001
Lecture Notes in Computer Science
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Ranga Vemuri. Working with him was a great learning opportunity for me. His guidance, suggestions and encouragement was the driving force for this work. I ...
In [21] , Ouaiss and Vemuri approach the problem using ILP formulation. They target memory mapping for RC architecture. ...
In [27] , Srinivasan and Vemuri handle the two problems at the same time. However, the memory mapping part is simplified and does not consider on-chip memories or multi-ported memories. ...
doi:10.1007/3-540-44687-7_8
fatcat:ggjaodw6wngkzkts6pcpq6kqgy
Architectural Power Estimation Based on Behavior Level Profiling
1998
VLSI design (Print)
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Ranga Vemuri, an associate professor of electrical and computer engineering at the University of Cincinnati, also directs its Laboratory for Digital Design Environments. ...
Vemuri received the M.Tech., degree from the Indian Institute of Technology, ...
doi:10.1155/1998/93106
fatcat:dbj3fnjmjncxvh4uli5dm56niu
Mitigating information leakage during critical communication using S*FSM
2019
IET Computers & Digital Techniques
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Security-centric components and systems, such as System-on-Chip early-boot communication protocols and ultraspecific lightweight devices, require a departure from minimalist design constructs. The need for built-in protection mechanisms, at all levels of design, is paramount to providing cost-effective, efficient, secure systems. In this work, Securely derived Finite State Machines (S*FSM) and power-aware S*FSM are proposed and studied. Overall results show that to provide an S*FSM, the typical
doi:10.1049/iet-cdt.2018.5186
fatcat:lvggujyjm5aajmeaxratqpppue
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... FSM requires a 50% increase in the number of states and a 57% increase in the number of product terms needed to define the state transitions. These increases translate to a minimum encoding space increase of 70%, raising the average encoding length from 4.8 bits to 7.9 bits. When factoring in relaxed structural constraints for power and space mitigation, the respective increases of 53 and 67% raise the average number of bits needed to 7.3 and 7.9. Regarding power savings, current minimisation is possible for both FSMs and S*FSMs through the addition of encoding constraints with average current reductions of 30 and 70%, respectively. Overall, a power-constrained S*FSM consumes about 5% more power than insecure FSMs with binary encodings, though with a penalty of a 95% increase in layout area.
Reverse Engineering Word-Level Models from Look-Up Table Netlists
[article]
2023
arXiv
pre-print
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Reverse engineering of FPGA designs from bitstreams to RTL models aids in understanding the high level functionality of the design and for validating and reconstructing legacy designs. Fast carry-chains are commonly used in synthesis of operators in FPGA designs. We propose a method to detect word-level structures by analyzing these carry-chains in LUT (Look-Up Table) level netlists. We also present methods to adapt existing techniques to identify combinational operations and sequential modules
arXiv:2303.02762v1
fatcat:5uj5bedohjaxtg22melxiccnum
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... in ASIC netlists to LUT netlists. All developed and adapted techniques are consolidated into an integrated tool-chain to aid in reverse engineering of word-level designs from LUT-level netlists. When evaluated on a set of real-world designs, the tool-chain infers 34\% to 100\% of the elements in the netlist to be part of a known word-level operation or a known sequential module.
Interconnect synthesis for reconfigurable multi-FPGA architectures
[chapter]
1999
Lecture Notes in Computer Science
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Most recon gurable multi-fpga architectures have a programmable interconnection network that can be recon gured to implement di erent i n terconnection patterns between the fpgas and memory devices on the board. Partitioning tools for such architectures must produce the necessary pin-assignments and interconnect con guration stream that correctly implement the partitioned design. We call this process Interconnect Synthesis for recon gurable architectures. The primary contribution of this paper
doi:10.1007/bfb0097943
fatcat:e76cwanlfnaglphtrqwpkrrpf4
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... s a interconnection synthesis technique that is independent of the recon gurable interconnection architecture. We h a ve developed an automatic interconnect synthesis tool that is based on Boolean satis ability. The target interconnection architecture is modeled in an architecture speci cation language. The desired interconnections among the fpgas are speci ed as in the form of a netlist. The tool automatically generates the pin-assignments and the required values for the con guration-inputs in the architecture speci cation. We modeled several recon gurable architectures and performed interconnect synthesis for varying number of desired nets. We provide experimental results that demonstrate the e ectiveness of the interconnection synthesis technique.
A performance modeling and analysis environment for reconfigurable computers
[chapter]
1998
Lecture Notes in Computer Science
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In many of the various layers of software supporting recongurable architectures such as compilers, operating systems, synthesis tools, and so forth, a primary objective is to deliver the performance, power, cost, and other advantages of recon gurable architectures to a target application. Inherent to these tools are various estimation procedures for such performance metrics as throughput time, power, reliability, cost, and so on. Analysis of Recon gurable Computers ARC is a comprehensive
doi:10.1007/3-540-64359-1_667
fatcat:wiwleeo7brhgnegwrb67drhs34
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... s and modeling tool we are developing that can be used to calculate these and other performance metrics.
Verification of Basic Block Schedules Using RTL Transformations
[chapter]
2001
Lecture Notes in Computer Science
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We present an approach to aid in debugging/development of scheduling algorithm implementations. Our technique makes use of a sequence of a correctness-preserving RTL transformation called Register Transfer Split (RTS), to collectively perform the same task as that of a scheduler. Violation of the transformation precondition signals an error and the sequence of RTS transformations applied so far forms a trace which can be used for debugging purposes.
doi:10.1007/3-540-44798-9_16
fatcat:7kvo3dlvd5gbfkqgx43ipmxham
Word-Level Structure Identification In FPGA Designs Using Cell Proximity Information
[article]
2023
arXiv
pre-print
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Reverse engineering of FPGA based designs from the flattened LUT level netlist to high level RTL helps in verification of the design or in understanding legacy designs. We focus on flattened netlists for FPGA devices from Xilinx 7 series and Zynq 7000. We propose a design element grouping algorithm that makes use of the location information of the elements on the physical device after place and route. The proposed grouping algorithm gives clusters with average NMI of 0.73 for groupings
arXiv:2303.07405v1
fatcat:lsrzn4lfcneupgqes33ckebcbu
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... all element types. The benchmarks chosen include a range of designs from communication, arithmetic units, processors and DSP processing units.
A Self-learning Optimization Technique for Topology Design of Computer Networks
[chapter]
2008
Lecture Notes in Computer Science
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Topology design of computer networks is a constrained optimization problem for which exact solution approaches do not scale well. This paper introduces a self-learning, non-greedy optimization technique for network topology design. It generates new solutions based on the merit of the preceding ones. This is achieved by maintaining a solution library for all the variables. Based on certain heuristics, the library is updated after each set of generated solutions. The algorithm has been applied to
doi:10.1007/978-3-540-78761-7_5
fatcat:d5qkwk53tvefto6k6uombednlq
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... a MPLS-based IP network design problem. The network consists of a set of Label Edge Routers (LERs) routing the total traffic through a set of Label Switching Routers (LSRs) and interconnecting links. The design task consists of -1) assignment of user terminals to LERs; 2) placement of LERs; and 3) selection of the actually installed LSRs and their links, while distributing the traffic over the network. Results show that our techniques attain the optimal solution, as given by GNU solver -lp solve, effectively with minimum computational burden.
Accurate Performance Estimation using Circuit Matrix Models in Analog Circuit Synthesis
[chapter]
2009
IFIP International Federation for Information Processing
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Vemuri
Almitra Pradhan and Ranga Vemuri ...
Specification Estimated Actual Gain ≥ 14 dB 15.18 15.44 Bandwidth ≥ 2000 Hz 2409 2417 Center Frequency ≥ 2500 Hz 2590 2592 FP1 ≥ 200 Hz
273
273
FP2 ≤ 15000 Hz
12109
12103
Almitra Pradhan and Ranga ...
doi:10.1007/978-0-387-89558-1_8
fatcat:tekjl5lrvvfkpefzqngq25hi3a
Behavioral partitioning in the synthesis of mixed analog-digital systems
2001
Proceedings of the 38th conference on Design automation - DAC '01
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Doboli and Vemuri [7] build a block-level analog signal flow graph representation, ABLOX from VHDL-AMS specifications. ...
doi:10.1145/378239.378373
dblp:conf/dac/GanesanV01
fatcat:n7vsartmhrdkzefsml45rmphdi
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