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Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations
2008
ACM Transactions on Reconfigurable Technology and Systems
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This article presents two strategies for compensating within-die stochastic delay variability by using reconfiguration: reconfiguring the entire FPGA, and relocating subcircuits within an FPGA. ...
Field-Programmable Gate Arrays may be able to compensate for within-die delay variability, by judicious use of reconfigurability. ...
Assume there are K types of element of interest for parametric yield in an FPGA, L k elements of type k, and the delay through Parametric Yield Modeling and Simulations of FPGA Circuits · 10: 9 any given ...
doi:10.1145/1371579.1371582
fatcat:2d6jytwzvnamzcsbh4dbd2z2pm
Parametric yield in FPGAs due to within-die delay variations
2007
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays - FPGA '07
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This paper presents three reconfiguration-based strategies for compensating within-die stochastic delay variability in FPGAs: reconfiguring the entire FPGA, relocating subcircuits within an FPGA, and reconfiguring ...
The reconfigurability of Field-Programmable Gate Arrays presents the opportunity to compensate for within-die delay variability. ...
ACKNOWLEDGEMENTS The authors are grateful for the financial support of the UK Engineering and Physical Sciences Research Council (Platform Grant EP/C549481/1). Thanks also to Dr. R. ...
doi:10.1145/1216919.1216949
dblp:conf/fpga/SedcoleC07
fatcat:xrmjon4xgnemziqbcp56hra3hu
Statistical Timing and Power Optimization of Architecture and Device for FPGAs
2012
ACM Transactions on Reconfigurable Technology and Systems
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Considering both die-to-die and within-die variations in effective channel length, threshold voltage, and gate oxide thickness, we first develop closed-form models of chip-level FPGA leakage and timing ...
We then derive analytical yield models considering both leakage and timing variations, and use such models to evaluate the performance of FPGA device and architecture considering process variations. ...
The first contribution of this article is that we develop closed-form models of chiplevel leakage and timing variations considering both die-to-die and within-die variations. ...
doi:10.1145/2209285.2209288
fatcat:t7gzuhdxqfbt7k4kai5xqd7km4
OPTIMIZATION OF CLOCK TREE SYNTHESIS UNDER STOCHASTIC PROCESS VARIATION MODELING FOR MULTI-FPGA SYSTEMS
2013
American Journal of Applied Sciences
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In this age of scientific computing, the experiment models and evaluation is a commonly employed rendition of the simulation methods. ...
In addition to the optimality, the methods which depict underlying uncertainty in process variation. It is accomplished by adjusting number of samples on delay and wire width. ...
as local (within-die or intra-die). ...
doi:10.3844/ajassp.2013.1604.1615
fatcat:vtva4zcjdbhofa6pz5doqlnkim
High-performance bridge-style full adder structure
2008
Smart Structures, Devices, and Systems IV
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The performance of this adder in terms of power, delay, energy, and yield are investigated. ...
The simulation results of this structure will take into account the process variations for a 90 nm CMOS process and present results based on post-layout simulation using Cadence and Synopsys tools. ...
Generally, there are two types of process variations, inter-die (or die-to-die, D2D) and intra-die (or within-die, WID). ...
doi:10.1117/12.813924
fatcat:h3fubze6qnb55ort5w3f2nrf2y
Limit study of energy & delay benefits of component-specific routing
2012
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays - FPGA '12
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As feature sizes scale toward atomic limits, parameter variation continues to increase, leading to increased margins in both delay and energy. ...
To understand the potential benefit we might gain from component-specific mapping, we quantify the margins associated with parameter variation in FPGAs over a wide range of predictive technologies (45nm ...
Any opinions, findings, and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the National Science Foundation. ...
doi:10.1145/2145694.2145710
dblp:conf/fpga/MehtaRD12
fatcat:r4ia5kw3wbeejmf7aodeqtxgnq
Rapid FPGA delay characterization using clock synthesis and sparse sampling
2010
2010 IEEE International Test Conference
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After that, we exploit the spatial correlation of the delays across the FPGA die to measure a small subset of CUT delays from an array of CUTs and recover the remaining entries with high accuracy. ...
Using this representation, the minimum number of frequency samples is determined to accurately estimate the delay for each CUT within the 2D FPGA array. ...
The total process variation can be viewed as the sum of inter-die and intradie variations. Inter-die variations refer to differences among the devices on various dies and are constant within one die. ...
doi:10.1109/test.2010.5699248
dblp:conf/itc/MajzoobiDEK10
fatcat:zkev2dxxqffltgrzl4ttjsk5cu
Parametric yield management for 3D ICs
2008
ACM Journal on Emerging Technologies in Computing Systems
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In this paper we develop a model to quantify the impact of process variations on the parametric yield of 3D ICs, and then we propose a number of integration strategies that use a graph-theoretic framework ...
(and experimental results) on leakage modeling and leakage-constrained parametric yield improvement. ...
The fabrication yield of integrated circuits is divided into two categories: functional yield and parametric yield. ...
doi:10.1145/1412587.1412592
fatcat:olscsswmfbablc5v6liiqijysi
Robust low-power reconfigurable computing with a variation-aware preferential design approach
2014
2014 IEEE International Conference on IC Design & Technology
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The proposed mapping process considers the reliability map of a memory array and maps the important operations with respect to output quality to more reliable memory blocks under performance constraint ...
These platforms often use high-density memory array, which suffer from variation-induced parametric failures. ...
Impact of cell sizing on output quality The memory model as described in Section III was simulated with the skewed cell design for the same inter-die and intra-die variations. ...
doi:10.1109/icicdt.2014.6838621
dblp:conf/icicdt/PaulMB14
fatcat:kyfsyji4zvdtfetqobt24i4cqi
Profit Aware Circuit Design Under Process Variations Considering Speed Binning
2008
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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Experiments on a set of ISCAS'85 benchmarks show in average 19% improvement in profit for simultaneous sizing and bin boundary determination, considering both leakage power dissipation and delay bounds ...
In this paper, a profit-aware design metric is proposed to consider the overall merit of a design in terms of power and performance. ...
Statistical Delay Model To compute the delay distribution of a circuit based on the information of both die-to-die and within-die parameter variations, we have employed the statistical static timing analysis ...
doi:10.1109/tvlsi.2008.2000364
fatcat:cwi3upmrlvcgbmc5r3yfpztn5u
Yield maximization for system-level task assignment and configuration selection of configurable multiprocessors
2008
Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis - CODES/ISSS '08
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Due to increasing concern of WID variation, designers will have to choose configurations of processing cores that maximize yield of the system while not affecting performance and throughput constraints ...
We provide a case study of configurable Leon processors as the cores implemented on FPGA. ...
Now, both within-die (WID) and inter-die variations have become strong in the new generations of transistors. ...
doi:10.1145/1450135.1450192
dblp:conf/codes/SinghalOB08
fatcat:23ql6lvi5ndtjmo7yweeck3twe
Efficient Additive Statistical Leakage Estimation
2009
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Hence, for each incremental change of the circuit, the covariances between each pair of circuit elements need to be recalculated, which is inefficient. ...
In this paper, we proposed a simple additive polynomial leakage-variation model. With additivity, we can calculate chip leakage power and leakage power after incremental change very efficiently. ...
Bell for the helpful discussion and initial work. ...
doi:10.1109/tcad.2009.2030433
fatcat:rpmpibns5jbq5ex62uy5723mpi
Digital signal processing in bio-implantable systems: Design challenges and emerging solutions
2010
2nd Asia Symposium on Quality Electronic Design (ASQED)
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Besides, programmability of the device and security of the recorded information are desirable features, which need to be considered during the design of such systems. ...
Use of nanoscale technology shows tremendous benefits in implementing these advanced circuits due to dramatic improvement in integration density and power dissipation per operation. ...
With increasing die-to-die and within-die parameter variations in nanoscale technologies, maintaining high yield and reliability of operation in sub-threshold design is becoming a major challenge. ...
doi:10.1109/asqed.2010.5548247
fatcat:teb4dnt5ira77one3os524747q
Exploring regular fabrics to optimize the performance-cost trade-off
2003
Proceedings of the 40th conference on Design automation - DAC '03
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This paper discusses some of the trade-offs to consider for determination of how much regularity a particular IC or application can afford. ...
We believe that IC design and manufacturing can be made more affordable, and reliable, by removing some design and implementation flexibility and enforcing new forms of design regularity. ...
The authors would also like to thank Ruchir Puri and John Cohn of IBM for their technical contributions to various aspects of this project. ...
doi:10.1145/776028.776031
fatcat:u46heki3p5c4bkd3a7hsrov4xi
Exploring regular fabrics to optimize the performance-cost trade-off
2003
Proceedings of the 40th conference on Design automation - DAC '03
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This paper discusses some of the trade-offs to consider for determination of how much regularity a particular IC or application can afford. ...
We believe that IC design and manufacturing can be made more affordable, and reliable, by removing some design and implementation flexibility and enforcing new forms of design regularity. ...
The authors would also like to thank Ruchir Puri and John Cohn of IBM for their technical contributions to various aspects of this project. ...
doi:10.1145/775832.776031
dblp:conf/dac/PileggiSSGKKPRT03
fatcat:bz4alfdacvebtfbbns7henwdfe
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