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VFCC: A verification framework of cache coherence using parallel simulation
2013
2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)
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A cache coherence protocol is a vital component of a multiprocessor to maintain the data consistency. ...
In this paper, we proposed VFCC, which is a simulation framework to validate a cache-coherence protocol implementation of a commercial 64-bit superscalar multiprocessor. ...
A survey has shown that there are three major techniques based on state enumeration, (symbolic) model checking and symbolic state model [4] . ...
doi:10.1109/aspdac.2013.6509683
dblp:conf/aspdac/XiongYSXT13
fatcat:xmhppidqgrbgrdrqvlhz27vm5m
MCjammer
2008
Proceedings of the conference on Design, automation and test in Europe - DATE '08
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In this work we present a scalable approach to the verification of memory coherence protocols in large multi-core and multi-processor systems. ...
The agents can dynamically change the stimuli based on coverage and pressure observed during simulation. ...
The use of a distributed simplified model allows our approach to be more scalable, than techniques that are based on the full description of the system coherency protocol. ...
doi:10.1145/1403375.1403539
fatcat:76noqdjwtfgbdcxrliry7mfvbi
Post-silicon verification for cache coherence
2008
2008 IEEE International Conference on Computer Design
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We reproduce in our experiments a set of coherence protocol bugs based on published errata documents of commercial multicore designs, and show that CoSMa is highly effective in detecting them. ...
In this work we present CoSMa, a novel technology offering high coverage functional post-silicon validation of cache coherence protocols in multicore systems. ...
ACKNOWLEDGMENTS The authors would like to thank Matthew Fojtik, Bradley Dobbie and Andy Lin for their implementation of CoSMa in a quad-core Alpha design and the valuable feedback provided as a result ...
doi:10.1109/iccd.2008.4751884
dblp:conf/iccd/DeOrioBB08
fatcat:yywoovhcm5ezlg44tzz32xwd5e
A Model-Based Approach to Design Test Oracles for Memory Subsystems of Multicore Microprocessors
Подход к построению тестовых оракулов для подсистем памяти многоядерных микропроцессоров на основе моделей
2015
Proceedings of the Institute for System Programming of RAS
Подход к построению тестовых оракулов для подсистем памяти многоядерных микропроцессоров на основе моделей
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The paper describes a method for constructing test oracles for memory subsystems of multicore microprocessors. The method is based on using nondeterministic reference models of systems under test. ...
A cache line oracle is comprised of the operation oracles and responsible for checking requests to the given cache line. ...
State-of-the-art coherence protocols are complicated; their implementations in hardware is difficult and error-prone. Accordingly, thorough verification of memory subsystems is required [2] . ...
doi:10.15514/ispras-2015-27(3)-11
fatcat:qpixgqtj6fe3pkt6debrq6cj7y
State space reduction in modeling checking parameterized cache coherence protocol by two-dimensional abstraction
2012
Journal of Supercomputing
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An example of parameterized cache coherence protocol based on MESI illustrates how to produce a much smaller abstract model by TDA. ...
The state space explosion is the first hurdle while applying model-checking to scalable protocols. ...
Talupur's work on environment abstraction, and supported by the National Natural Science Foundation of China under Grant No. 61070036 and 61133007. ...
doi:10.1007/s11227-012-0755-0
fatcat:sxnedag54rhmdidwnh3bw6jiru
I'm done simulating; now what? Verification coverage analysis and correctness checking of the DEC chip 21164 Alpha microprocessor
1996
Proceedings of the 33rd annual conference on Design automation conference - DAC '96
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Special emphasis was placed on the tasks of checking for correct operation and functional wverage analysis. ...
This simulation-based verification effort used implementation-directed, pseudorandom excrchsers which were supplemented with implementationspecific, hand-generated tests. ...
For example, the system bus had ii complicated set of checkers attached to it that checked for violations of the bus protocol. ...
doi:10.1145/240518.240580
dblp:conf/dac/KantrowitzN96
fatcat:a3fvglx2hfclxik6tcwlwtxlke
Design experience of a chip multiprocessor merlot and expectation to functional verification
2002
Proceedings of the 15th international symposium on System Synthesis - ISSS '02
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We have successfully run parallelized mpeg3 decoder on the first silicon with several software workarounds, thanks to functional verification environment including system modeling on RTL. ...
On Merlot, multiple threads provide wider issue window beyond ordinal instruction level parallel (ILP) processors like superscalar or VLIW. ...
Specman reduces the verification cost with a test bench description language and verification IPs including constraint driven random generation, functional coverage analysis, and protocol checking. ...
doi:10.1145/581199.581223
fatcat:x36o4c62hbh7vaozjrpgrwzvte
Design experience of a chip multiprocessor merlot and expectation to functional verification
2002
Proceedings of the 15th international symposium on System Synthesis - ISSS '02
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We have successfully run parallelized mpeg3 decoder on the first silicon with several software workarounds, thanks to functional verification environment including system modeling on RTL. ...
On Merlot, multiple threads provide wider issue window beyond ordinal instruction level parallel (ILP) processors like superscalar or VLIW. ...
Specman reduces the verification cost with a test bench description language and verification IPs including constraint driven random generation, functional coverage analysis, and protocol checking. ...
doi:10.1145/581220.581223
fatcat:ylogpwxrprhafgn6jc2acch3vy
Functional verification of the POWER4 microprocessor and POWER4 multiprocessor systems
2002
IBM Journal of Research and Development
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The approach was hierarchical, based on but considerably expanding the practice used for verification of the CMOS-based IBM S/390 Parallel Enterprise Server TM G4. ...
Multi-unitlevel verification, performed on storage and I/O components as well as on the processor, confirmed architectural compliance for each of the chips and subsystems. ...
All tests run on the dyadic model were checked by CML for MP problems and protocol violations. ...
doi:10.1147/rd.461.0053
fatcat:474llttpkvghngwg4q6veuhvqq
Case Study: First-Time Success ASIC Design Methodology Applied to a Multi-Processor System-on-Chip
[chapter]
2018
Application Specific Integrated Circuits - Technologies, Digital Systems and Design Methodologies [Working Title]
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RUMPS401 SDR-based transceiver test result. Case Study: First-Time Success ASIC Design Methodology Applied to a Multi-Processor System-on-Chip ...
At the front end part of the methodology, the end is the equivalence check process and the resulting netlist from the process is then passed for the back end step. ...
Each UVC is designed for a specific design or protocol. It generates stimulus, performs checking and collects coverage information. ...
doi:10.5772/intechopen.79855
fatcat:vff3ewqmmzfnrpxgr2eyo2g5ye
Verification strategy for the Blue Gene/L chip
2005
IBM Journal of Research and Development
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The verification platform is based on event simulation and cycle simulation running on a farm of Intel-processor-based machines, several PowerPCprocessor-based machines, and the internally developed hardware ...
System-on-a-chip verification problems require a multilevel verification strategy in which the strengths of each layer offset the weaknesses of another layer. ...
Acknowledgment The Blue Gene/L project has been supported and partially funded by the Lawrence Livermore National Laboratory on behalf of the United States Department of Energy under Lawrence Livermore ...
doi:10.1147/rd.492.0303
fatcat:u2v6x36e3zekrgafkfrfcukfzq
Dacota: Post-silicon validation of the memory subsystem in multi-core designs
2009
2009 IEEE 15th International Symposium on High Performance Computer Architecture
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verification tasks that are executed directly on prototype hardware. ...
Logs are periodically aggregated and checked by a distributed algorithm running in-situ on the CMP to verify correct memory operation ordering. ...
The MOESI directory protocol was used as the coherence protocol, along with the Total Store Ordering consistency model. ...
doi:10.1109/hpca.2009.4798278
dblp:conf/hpca/DeOrioWB09
fatcat:33h2gkvx3vf6toxhl4t2t2nh5q
Functional verification of the z990 superscalar, multibook microprocessor complex
2004
IBM Journal of Research and Development
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Since the methods used at system-level verification were much the same as the ones used on the CMOS-based IBM S/390 Parallel Enterprise Server G4, the focus of this paper is on the work done at the unit ...
The verification process started at the unit level, which focused on the correctness of the microarchitecture, and then proceeded to the element level to verify the architectural correctness of the microprocessor ...
Acknowledgments The authors acknowledge all z990 design team members and other individuals throughout IBM for their contributions to the verification effort. ...
doi:10.1147/rd.483.0347
fatcat:c7pqoghcxzawbpgskfqe3jvs4y
Strategic directions in concurrency research
1996
ACM Computing Surveys
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-Requirements verification: model checking, proof checking, behavioral relation checking. ...
For example, an approach to design and verification based on a true concurrency model may yield greater computational efficacy than one based on interleaving, since the former admits the application of ...
doi:10.1145/242223.242252
fatcat:4gu2wurduveqdhqqrhr27yaqjq
Distance-Guided Hybrid Verification with GUIDO
2006
Proceedings of the Design Automation & Test in Europe Conference
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Constrained random simulation is a widespread technique used to perform functional verification on complex digital designs, because it can generate simulation vectors at a very high rate. ...
However, the generation of high-coverage tests remains a major challenge even in light of this high performance. ...
[1] , where theorem-proving techniques are used to coordinate multiple model checking runs. An approach of a guided counter-example generation based on abstraction was proposed in [6] . ...
doi:10.1109/date.2006.244050
dblp:conf/date/ShyamB06
fatcat:ypwekabajvdqfec3vky72g6fgm
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