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ENBB Processor: Towards the ExaScale Numerical Brain Box [Position Paper]
[article]
2019
arXiv
pre-print
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We expect to reduce significantly the needs of main memory due to the execution model proposed, where variables are just virtual interconnections in the network or signals stored in the virtual channels ...
This may lead to systems composed of microprocessors with main memory incorporated in 3D chips. ...
The virtual channels (storage in each switch) should provide the necessary support for the control flow policy (communication), and also would be used as internal storage of data for the microprocessor ...
arXiv:1902.06655v1
fatcat:niubzoi7cjfv5fxeykfeocg5em
NANA
2006
ACM Journal on Emerging Technologies in Computing Systems
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This architecture represents an initial, unoptimized solution for understanding the implications of DNA-guide self-assembly. ...
The specific nanotechnology we explore proposes patterned DNA nanostructures as a scaffold for the placement and interconnection of carbon nanotube or silicon nanorod FETs to create a limited size circuit ...
Random node orientation. Similar to the random node placement, the assembly process we envision does not provide control over node orientation. ...
doi:10.1145/1126257.1126258
fatcat:fflt2woivzf6dco33fwn46o2d4
PIM-enabled instructions
2015
SIGARCH Computer Architecture News
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Processing-in-memory (PIM) is rapidly rising as a viable solution for the memory wall crisis, rebounding from its unsuccessful attempts in 1990s due to practicality concerns, which are alleviated with ...
This allows PIM operations to be interoperable with existing programming models, cache coherence protocols, and virtual memory mechanisms with no modification. ...
10041608, Embedded System Software for New Memory-based Smart Devices). ...
doi:10.1145/2872887.2750385
fatcat:ckgc7e3kxrcdlde6z32e3vxsu4
PIM-enabled instructions
2015
Proceedings of the 42nd Annual International Symposium on Computer Architecture - ISCA '15
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Processing-in-memory (PIM) is rapidly rising as a viable solution for the memory wall crisis, rebounding from its unsuccessful attempts in 1990s due to practicality concerns, which are alleviated with ...
This allows PIM operations to be interoperable with existing programming models, cache coherence protocols, and virtual memory mechanisms with no modification. ...
10041608, Embedded System Software for New Memory-based Smart Devices). ...
doi:10.1145/2749469.2750385
dblp:conf/isca/AhnYMC15
fatcat:j5lepsilqfedzdxp2iu5ozbvji
HiPE on AMD64
2004
Proceedings of the 2004 ACM SIGPLAN workshop on Erlang - ERLANG '04
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Even though Erlang/OTP is by default based on a virtual machine interpreter, it nowadays also includes the HiPE (High Performance Erlang) native code compiler as a fully integrated component. ...
Erlang is a concurrent functional language designed for developing large-scale, distributed, fault-tolerant systems. The primary implementation of the language is the Erlang/OTP system from Ericsson. ...
AMD64 supports both x87 and the register-oriented SSE2 floating-point unit, with SSE2 being preferred for new code. ...
doi:10.1145/1022471.1022478
dblp:conf/erlang/LunaPS04
fatcat:7e7rtafj5jcp7nrln7k7jpnpde
SYMBOL
1971
Proceedings of the May 18-20, 1971, spring joint computer conference on - AFIPS '71 (Spring)
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The authors wish to acknowledge George Powers, Stanley Mazor, and Russel Briggs for their contributions to the hardware development and Hamilton ...
The Memory Reclaimer (MR) supports the MC by reprocessing used space to make it available for subsequent reuse. ...
control exchange cycles
Figure 4 - 4 The simple two level addressing structure for the virtual memory
Figure 5 - 5 Virtual memory organization showing the fixed location of pages in the paging memory ...
doi:10.1145/1478786.1478869
dblp:conf/afips/SmithRCLLCGC71
fatcat:uevai6ccdrcphjbgnbauuirnem
Defeating return-oriented rootkits with "Return-Less" kernels
2010
Proceedings of the 5th European conference on Computer systems - EuroSys '10
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Without the need of injecting their own malicious code, these rootkits can discover and chain together "return-oriented gadgets" (that consist of only legitimate kernel code) for rootkit computation. ...
Recent efforts have made significant progress in blocking them from injecting malicious code into the OS kernel for execution. ...
Tran, Emre Can Sezer, and Ahmed Moneeb Azab for the helpful discussion. ...
doi:10.1145/1755913.1755934
dblp:conf/eurosys/LiWJGB10
fatcat:ucuv4xzdvrfvhjqciud4guky4a
The Delft-Java Engine
[chapter]
2002
Java Microarchitectures
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A computer system supporting N different machine views, where N.gtoreq.2, includes a memory for storing instructions, a number of execution units for processing data based on execution controls, and N ...
Control Switching: The JAVA Virtual Machine contains no support for interruption, humble access or dispatching. State Saving: The JAVA Virtual Machine contains no support for context switching. ...
Biography for C. John Glossner  ohn Glossner is currently CTO and Executive Vice President of Engineering at Sandbridge Technologies, Inc. ...
doi:10.1007/978-1-4615-0993-6_6
fatcat:67xqmkixtva7nbrqcuwlh2e5wu
DVM: A Big Virtual Machine for Cloud Computing
2014
IEEE transactions on computers
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tasks run concurrently in a large, unified, and snapshotted memory space. ...
Along with an efficient execution engine, the capacity of a DVM can scale up to support large clusters. ...
We thank the Amazon AWS research grant and the Guangzhou Supercomputing Center for the support in the EC2 and TH-1/GZ based evaluation. ...
doi:10.1109/tc.2013.102
fatcat:crcpla42i5cetg7th7epc35mzm
Packet-driven General Purpose Instruction Execution on Communication-based Architectures
2010
Journal of Integrated Circuits and Systems
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This paper addresses the main architectural concerns involved on creating datapaths for routers as well as the programming model suggested to pack instructions on messages. ...
This architecture is thus not intended to be a stand-alone solution, rather an IP core accelerator for data oriented intensive computing, which would take place in a SoC. ...
In this figure, it showed that LOAD needs only one operand, the memory address. ...
doi:10.29292/jics.v5i1.310
fatcat:whel4vekajf5fiomjceaxooc3i
The "MIND" scalable PIM architecture
[chapter]
2005
Advances in Parallel Computing
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MIND (Memory, Intelligence, and Network Device) is an advanced parallel computer architecture for high performance computing and scalable embedded processing. ...
MIND is multicore with multiple memory/processor nodes on each chip and supports global shared memory across systems of MIND components. ...
Henri Cassanova of UCSD for his substantial contributions in editing this document. ...
doi:10.1016/s0927-5452(05)80010-3
fatcat:m7w6wqjxjrg3zowstdubiknvne
picoJava-I: the Java virtual machine in hardware
1997
IEEE Micro
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The compiler itself along with the memory footprint for the compilation may require a few megabytes of storage. ...
Interpretation is simple, does not require much memory, and is relatively easy to implement on an existing processor. ...
In addition, we thank members of the management team-specifically Shrenik Mehta and Robert Garner-and the people at JavaSoft for their help. Key members of the picoJava-I design team at Sun are R. ...
doi:10.1109/40.592314
fatcat:efalm3dkcjbr7oaagg6b6ug3wu
Micro Spitbol
[article]
2013
arXiv
pre-print
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A compact version of MACRO SPITBOL, a compiler/ interpreter for a variant of SNOBOL4, has been developed for use on microcomputer systems. ...
The techniques for producing an implementation are largely automatic in order to preserve the integrity and portability of the SPITBOL system. ...
It supports up to 65K bytes of magnetic core memory with a cycle time of 1.6 microseconds. ...
arXiv:1308.6096v1
fatcat:56vop7k4tbdvrhlzt7xblydnc4
Distributed Memo: A Heterogeneously Distributed and Parallel Software Development Environment
1994
1994 International Conference on Parallel Processing (ICPP'94)
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Object oriented technology is exploited to provide this seamless environment. ...
This integration provides a conducive environment for parallel and distributed application development, by abstracting the issues of hardware and communication. ...
Parallel Virtual Machine (PVM) is a low-level approach taken to support the virtual machine concept [11] . A system service is provided for each machine on a heterogeneous network. ...
doi:10.1109/icpp.1994.94
dblp:conf/icpp/OConnellTC94
fatcat:eapfd4msljekxfz2ydnxdfjnaa
DVM
2012
Proceedings of the 8th ACM SIGPLAN/SIGOPS conference on Virtual Execution Environments - VEE '12
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tasks run concurrently in a large, unified, and snapshotted memory space. ...
Along with an efficient execution engine, the capacity of a DVM can scale up to support large clusters. ...
We thank Yanling Zheng, Mengmeng Cheng, Chengqi Song and Yanqun Zhang for their help in various aspects of this project, and the Amazon AWS research grant for the support in the EC2 based evaluation. ...
doi:10.1145/2151024.2151032
dblp:conf/vee/MaSGWZ12
fatcat:xykdqu64cvfklco5tt5pycy7b4
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