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Energy Model of Networks-on-Chip and a Bus
2005
2005 International Symposium on System-on-Chip
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A Network-on-Chip (NoC) is an energy-efficient onchip communication architecture for Multi-Processor Systemon-Chip (MPSoC) architectures. ...
In earlier papers we proposed two Network-on-Chip architectures based on packet-switching and circuit-switching. ...
ACKNOWLEDGEMENT This research is conducted within the Smart Chips for Smart Surroundings project (IST-001908) supported by the Sixth Framework Programme of the European Community. ...
doi:10.1109/issoc.2005.1595650
dblp:conf/issoc/WolkotteSKBB05
fatcat:wborsjqvevaaxh5pwyii6p65vu
An Embedded Language Approach to Router Specification in Curry
[chapter]
2004
Lecture Notes in Computer Science
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It includes a specification language with features for declaring and connecting router elements and for designing abstractions. ...
Recently, a modular architecture and toolkit for building software routers and other packet processors has been introduced: the Click system. ...
Acknowledgments We would like to thank Eddie Kohler for useful comments and suggestions. ...
doi:10.1007/978-3-540-24618-3_24
fatcat:xqzfdkxgjfei5k5632vtxfuj3a
Fast scalable FPGA-based Network-on-Chip simulation models
2011
Ninth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMPCODE2011)
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of magnitude speedup, depending on the network and router configuration. ...
For smaller networks and simpler router configurations a directmapped approach was employed, where the network to be simulated was directly implemented on the FPGA. ...
We thank Xilinx for their FPGA and tool donations. We thank Bluespec for their tool donations and support. ...
doi:10.1109/memcod.2011.5970513
dblp:conf/memocode/Papamichael11
fatcat:j4cpckjovjf6tgkerjplpmkhtq
Test results of the commercial internet multimedia trials
1998
Computer communication review
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Network Testing The search for customers, applications and application tools began concurrently with setting up the test beds. There were three test beds. ...
The Test Beds MCI's SMDS network supported a multi-site test bed for multicast and RSVP evaluation. Each of the sites was connected with a DS1 circuit to the SMDS network. ...
The authors also thank Christian Maciocco, John Richardson and the anonymous reviewer for their comments on previous drafts of this paper. ...
doi:10.1145/280549.280553
fatcat:46eby6y45vfzlek5kriwd7nfpy
System-Level Modeling of a NoC-Based H.264 Decoder
2008
2008 2nd Annual IEEE Systems Conference
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Networks-on-chip (NoC) are expected to play a key role in future embedded systems. A NoC-based system has the potential to support concurrent processing, in both software and hardware. ...
We show latency, area, and power consumption results for this NoC architecture abstracted from its FPGA implementation. ...
To overcome such failures, one would have to develop abstract concurrency models and do exhaustive analysis on these models to test for concurrency problems. ...
doi:10.1109/systems.2008.4519008
fatcat:skisjbza45fodg4ffip4z3yxcy
Network Element Testing Using TTCN-3: Benefits and Comparison
[chapter]
2005
Lecture Notes in Computer Science
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TTCN-3 (Testing and Test Control Notation), developed at ETSI and standardized by the ITU-T, enables testers to specify test cases for the various types of testing, and supports reuse of test artifacts ...
This paper presents the benefits we have observed during system development and provides a comparison with other testing practices deployed in our organization. ...
The results of an earlier pilot project in protocol implementation encouraged us to rely on TTCN-3 and supporting tools for the development of a major release of a telecommunication system. ...
doi:10.1007/11506843_19
fatcat:rf4iplsdk5febm4la2sepbeome
A Device-Independent Router Model
2008
IEEE INFOCOM 2008 - The 27th Conference on Computer Communications
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We construct a profiling tool and use it to derive router parameter tables within a few hours. Our preliminary results indicate that our model can approximate the Cisco routers. ...
Several popular simulation and emulation environments fail to account for realistic packet forwarding behaviors of commercial switches and routers. ...
We did not directly use the ns-2 emulation code as it does not support sending/receiving spoofed IPs (required for subnet emulation on a single node), and it is data-rate limited. ...
doi:10.1109/infocom.2008.225
dblp:conf/infocom/ChertovFS08
fatcat:by7e72qqzjetzfavv7ryiobd4y
A Device-Independent Router Model
2008
2008 Proceedings IEEE INFOCOM - The 27th Conference on Computer Communications
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We construct a profiling tool and use it to derive router parameter tables within a few hours. Our preliminary results indicate that our model can approximate the Cisco routers. ...
Several popular simulation and emulation environments fail to account for realistic packet forwarding behaviors of commercial switches and routers. ...
We did not directly use the ns-2 emulation code as it does not support sending/receiving spoofed IPs (required for subnet emulation on a single node), and it is data-rate limited. ...
doi:10.1109/infocom.2007.225
fatcat:ybbztcaltfhazmojyj3e7chwbm
AN OCTA-CORE PROCESSOR WITH SHARED MEMORY AND MESSAGE-PASSING
2015
International Journal of Research in Engineering and Technology
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For verification and functionality test of above fully synthesized multi core processor, matrix multiplication operation is mapped onto the above said. ...
The router is four stage pipelined supporting DOR X-Y routing algorithm and with round robin arbitration technique. ...
Belorkar and the whole staff of EXTC Dept. of HVPM's CoET for providing the essential resources and environment. ...
doi:10.15623/ijret.2015.0405071
fatcat:ef5cooni2nezfhbbiqegp7jgdi
Filter Router: An Enhanced Router Design for Efficient Stacked Shared Cache Network
2019
IEICE Electronics Express
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And then, a meshed router network integrated with enhanced routers is proposed for fast identification of target accesses and further handling them. ...
Hence, the experimental results show that our network design can achieve an average improvement of 26.1 percent on speedup IPC and an average saving of 9.7 percent on energy consumption over base system ...
Zhang Xiaoyang (Synopsys Shanghai) who had fully supported on router layout. This work is partly supported by GJJ180486. ...
doi:10.1587/elex.16.20190358
fatcat:irmn6ragkzhsri7t7uunzegg3e
Designing a GENI Experimenter Tool to Support the Choice Net Internet Architecture
2014
2014 IEEE 22nd International Conference on Network Protocols
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and compiling node-specific code, executing Click modules, running commands on sets of nodes, accessing the local file system on nodes, and dynamically logging into nodes. ...
However, we found that GENI currently lacks the tools needed to make it easy to use these features. ...
Systems such as the GENI Desktop [20] are focused on providing instrumentation and measurement support, with only minimal support for setup and configuration or runtime control of an experiment. ...
doi:10.1109/icnp.2014.88
dblp:conf/icnp/BrownANCGC14
fatcat:75dz4iqsi5bg3g2pqq3tbvrhbq
Flexible distributed testbed for high performance network evaluation
2006
2nd International Conference on Testbeds and Research Infrastructures for the Development of Networks and Communities, 2006. TRIDENTCOM 2006.
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The arrangements allows for the rapid and automated configuration of various network scenarios. ...
In addition, the use of IP tunnelling allows testbed islands to be interconnected in support of larger distributed arrangements. ...
ACKNOWLEDGEMENTS This work was partially supported by the Spanish Research Council (CICYT) under contract TIC2003-05567. ...
doi:10.1109/tridnt.2006.1649199
fatcat:havk4pnimndhxizrqvzow3sgg4
Building a flexible and scalable DRAM interface for networking applications on FPGAs
2006
Proceedings of the internation symposium on Field programmable gate arrays - FPGA'06
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We quantify the various challenges and present techniques that were implemented to build a flexible and scalable interface to an existing multi-port memory controller for DDR DRAM using a FPGA. ...
This paper presents a study that attempts to overcome this challenge for networking application domain. ...
test throughput of the memory sub-system. ...
doi:10.1145/1117201.1117258
dblp:conf/fpga/ChongKB06
fatcat:l6ovxc4rnzhtpfs3jebzsapyui
Hey Fellows, We Shrunk the Server
2012
International Journal of Online Engineering (iJOE)
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This lab is based on open source software and on a cheap router with OpenWrt firmware, a Linux distribution targeted at embedded systems, which acts as a processing unity. ...
In this paper, a remote lab for the test of printed circuit boards and the programming/configuration of programmable logic devices and memories through a JTAG interface is presented. ...
ACKNOWLEDGMENT The authors would like to thank Paulo Matos and Jaime Neto from DEI-ISEP for their help in recycling hardware resources on the initial phase of this work. ...
doi:10.3991/ijoe.v8is2.1960
fatcat:adk7krezlrglzbxvkhsytqtcvu
Message-Passing Concurrency for Scalable, Stateful, Reconfigurable Middleware
[chapter]
2012
Lecture Notes in Computer Science
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Message-passing concurrency (MPC) is increasingly being used to build systems software that scales well on multi-core hardware. ...
A limitation of existing programming models and frameworks that support dynamic reconfiguration for stateful middleware, such as component frameworks, is that they are not designed for MPC. ...
The main reasons for the renewed interest in MPC are that it scales well on multi-core hardware architectures and that it provides a simple and compositional concurrent programming model, free from the ...
doi:10.1007/978-3-642-35170-9_11
fatcat:km5adcjd3bg5hg6e5u7pftsl4q
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