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Obfuscating DSP Circuits via High-Level Transformations
2015
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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Structural obfuscation is also achieved by the proposed methodology via high-level transformations. ...
This paper presents a novel approach to design obfuscated circuits for digital signal processing (DSP) applications using high-level transformations, a key-based obfuscating finite-state machine (FSM), ...
This paper, for the first time, presents design of obfuscated DSP circuits via high-level transformations that are harder to reverse engineer. ...
doi:10.1109/tvlsi.2014.2323976
fatcat:2dgji6k57zh4hh7xva2uvrsy7a
Protecting DSP circuits through obfuscation
2014
2014 IEEE International Symposium on Circuits and Systems (ISCAS)
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This paper presents a novel approach to protect digital signal processing (DSP) circuits through obfuscation by using high-level transformations. ...
The goal is to design DSP circuits that are harder to reverse engineer. High-level transformations of iterative data-flow graphs have been exploited for area-speed-power tradeoffs. ...
OBFUSCATION VIA HIGH-LEVEL TRANSFORMATIONS
A. ...
doi:10.1109/iscas.2014.6865256
dblp:conf/iscas/LaoP14
fatcat:nujoytetczf6xbv4mgozlfysji
Hardware Obfuscation Driven by QR Pattern using High Level Transformations
2019
International Journal of Advanced Trends in Computer Science and Engineering
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The experimental evaluation is carried out for proving the logic obfuscation method using FIR DSP digital design. ...
Experimental evaluations demonstrate the low area, power, and trade off the performance over security level of the proposed obfuscation technique. ...
In this work, for the first time, we presents color QR pattern to obfuscate the DSP circuits via FSM state transformations which are harder to reverse engineer. ...
doi:10.30534/ijatcse/2019/0881.32019
fatcat:lf7zjbpnfzd7nozcanibgjxwim
Mode-based Obfuscation using Control-Flow Modifications
2016
Proceedings of the Third Workshop on Cryptography and Security in Computing Systems - CS2 '16
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• No existing methods of obfuscation target these specific
concerns.
Basic concepts
• Folding:
High-level transformation on circuits to create time-multiplexed
architectures. ...
parts in circulation, according to a 2010 estimate
by SMT Corp., based in Sandy Hook, Conn)*
Goals of obfuscation
• Address obfuscation of Digital Signal Processing (DSP) circuits ...
Analysis of Obfuscated Modes Obscurity of control-flow : • For C different control signals in the design, each is obfuscated to degree L using a L:1 mux. ...
doi:10.1145/2858930.2858934
dblp:conf/hipeac/KoteshwaraKP16
fatcat:6w4ex5j7sjd2zmni7xns5px3vq
Obfuscation Mechanism for DSP Protection
2020
International Journal of Engineering Research and
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The aim of the paper is to obfuscate the DSP circuits by using HLT transformations. By the obfuscation, we protect the hardware. The image scaling algorithms employed for confounding the circuits. ...
The design aims at the HLT(high-level transformations) of repeated state graphs which have been utilized for speed, area and power compromises. ...
applicable high-level transformation ought to be chosen consistent with the performance demand.Step3: Obfuscation via HLT techniques: -Suitable HLT techniques are applied. ...
doi:10.17577/ijertv9is050050
fatcat:q6i5gwr5fbh2dcpjqns23psetq
2020 Index IEEE Transactions on Consumer Electronics Vol. 66
2020
IEEE transactions on consumer electronics
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Wang, G., +, T-CE
Aug. 2020 261-270
Integrated circuit design
Enhanced Security of DSP Circuits Using Multi-Key Based Structural
Obfuscation and Physical-Level Watermarking for Consumer Electronics ...
Sengupta, A., +, T-CE May 2020 163-172
Integrated circuit yield
Enhanced Security of DSP Circuits Using Multi-Key Based Structural
Obfuscation and Physical-Level Watermarking for Consumer Electronics ...
doi:10.1109/tce.2020.3043154
fatcat:omfsm4ecsbfa5j62upx2p3w44y
TAO: Techniques for Algorithm-Level Obfuscation during High-Level Synthesis
2018
2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)
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We propose TAO as a comprehensive solution based on high-level synthesis to raise the abstraction level and apply algorithmic obfuscation automatically. ...
Finally, this is a promising approach to obfuscate large-scale designs despite the hardware overhead needed to implement the obfuscation. ...
High-level transformations have been already proposed but only to obfuscate DSP circuits [9] . SAT-based attacks can extract these keys [16, 18] . ...
doi:10.1109/dac.2018.8465830
fatcat:l2lcr5yhorcfraxabwqbrd3clu
2019 Index IEEE Transactions on Consumer Electronics Vol. 65
2019
IEEE transactions on consumer electronics
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Groba, A.M., +, T-CE Feb. 2019 18-27
Protecting DSP Kernels Using Robust Hologram-Based Obfuscation. ...
Yanambaka, V.P., +,
T-CE Aug. 2019 388-397
Protecting DSP Kernels Using Robust Hologram-Based Obfuscation. ...
doi:10.1109/tce.2019.2952223
fatcat:y4lvedb7gbd3fbkzpnjhd5xt2i
Preventing Distillation-based Attacks on Neural Network IP
[article]
2022
arXiv
pre-print
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Moreover, the accuracy and prediction distributions are maintained, no functionality is disturbed, nor are high overheads incurred. ...
We elaborate a threat model which highlights the difference between random logic obfuscation and the obfuscation of NN IP. ...
In the second stage, the NN IP is typically converted from a high-level model to a C/C++ description [12] . In the third stage, the NN IP is obfuscated with poisoning the predictions. ...
arXiv:2204.00292v1
fatcat:oukjsnwbsjdgzkhyi6iu6rgvwu
Survey of hardware protection of design data for integrated circuits and intellectual properties
2014
IET Computers & Digital Techniques
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However, several published works propose different ways to protect design data including functional locking, hardware obfuscation, and IC/IP identification. ...
Over the past ten years, the designers of integrated circuits and intellectual properties have faced increasing threats including counterfeiting, reverse-engineering and theft. ...
Obfuscation/camouflaging
Symmetric and asymmetric
ciphering
3 900 slices
N/C
Xilinx Virtex IV
[67]
2008
Obfuscation/camouflaging
Key exchange via heat
225 slices
0,5mW
Xilinx Spartan 3A ...
doi:10.1049/iet-cdt.2014.0028
fatcat:c2gzjh2mkbf7tjifyd44lrvrru
Secure and Reliable Biometric Access Control for Resource-Constrained Systems and IoT
[article]
2018
arXiv
pre-print
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Aside from reducing the risk of compromising the biometric, the nature of obfuscation also provides protection against access control circumvention via malware and fault injection. ...
Second, a major requirement of the proposed PUF/obfuscation approach is that a reliable (robust) key be generated from the users input biometric. ...
An example of system-level obfuscation is presented in Fig. 1(b) . The key-controlled multiplexer (question mark box) conceals the interconnections among integrated circuits (ICs). ...
arXiv:1803.09710v1
fatcat:5c3s5oiqgbep7cpwzkeioluzpi
2019 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 38
2019
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Zhu, W., +, TCAD July 2019 1278-1290 High level synthesis ACHILLES: Accuracy-Aware High-Level Synthesis Considering Online Quality Management. ...
A Study on the State of High-Level Synthesis. Lahti, S., +, TCAD May 2019 898-911 Hybrid Quick Error Detection: Validation and Debug of SoCs Through High-Level Synthesis. ...
doi:10.1109/tcad.2020.2964359
fatcat:qjr6i73tkrgnrkkmtjexbxberm
A survey of hardware Trojan threat and defense
2016
Integration
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Therefore, it is very important to analyze the specific HT threats existing in the whole life cycle of integrated circuits (ICs), and perform protection against hardware Trojans. ...
Logic obfuscation Logic obfuscation (LO) is a probabilistic transform O that converts a source circuit F into a new circuit O(F) that has the same functionality as F but less intelligible in some senses ...
Sequential logic obfuscation is another way to obfuscate IC designs by adding new states and transformations in the finite state machine (FSM) [71] [72] [73] . ...
doi:10.1016/j.vlsi.2016.01.004
fatcat:fms3p3j7m5f7flfpewrgbz5bpy
A Survey on Chip to System Reverse Engineering
2016
ACM Journal on Emerging Technologies in Computing Systems
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In this paper, we will be presenting a survey of reverse engineering and anti-reverse engineering techniques on the chip, board, and system levels. ...
[Li et al. 2012 ] present RE of gate-level netlists to derive the high-level function of circuit components based on behavioral pattern mining. ...
High-Level Netlist Extraction from Gate-Level Schematic. ...
doi:10.1145/2755563
fatcat:uzdampyd6fc2fg2axhn7ydnioi
Multi-Tenant Cloud FPGA: A Survey on Security
[article]
2022
arXiv
pre-print
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Hardware obfuscation or camouflage is a unique approach to obfuscate tenant circuits from malicious attackers. ...
However, the improvement and development of high-level-synthesis (HLS) design tools e.g. ...
arXiv:2209.11158v1
fatcat:lncjxjjqhvbzznyihuxppo2i4e
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