A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2018; you can also visit the original URL.
The file type is application/pdf.
Filters
Testing Technique of BIST: A Survey
2017
International Journal of Computer Applications
Preserved Fulltext
As the compactness of system-on-chip (SoC) increase, it becomes striking to integrate dedicated test logic on a chip. ...
Starting with a broad idea of test problems, this survey paper focus on "Chip" Built in Self-Test (BIST) study and its promotion for board and system-level applications. ...
Efficient reduce the More Huang Parallel hardware Complexity Transparent overhead and High BIST without power Method for losing fault requirement Multiple coverage Embedded Memory Buffers Jinkyu LFSR Reduce ...
doi:10.5120/ijca2017913133
fatcat:jpajhgrbxncwfnndzezx77bniq
Software-based self-testing methodology for processor cores
2001
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2005; you can also visit the original URL.
The file type is application/pdf.
Application of the novel software-based self-test method demonstrates its significant cost/fault coverage benefits and its ability to apply at-speed test while alleviating the need for high-speed testers ...
During the process of self-test, the test generation program expands the self-test signatures into test sets and the test application program applies the tests to the components under test at the speed ...
ACKNOWLEDGMENT The authors would like to thank P. Sanchez and K. Sekar for their help with the picoJava processor core. ...
doi:10.1109/43.913755
fatcat:ors6roeymfgq5mmozi2mgg52te
Embedded hardware and software self-testing methodologies for processor cores
2000
Proceedings of the 37th conference on Design automation - DAC '00
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2005; you can also visit the original URL.
The file type is application/pdf.
Application of the novel softwarebased self-test method demonstrates its significant cost/fault coverage benefits and its ability to apply at-speed test while alleviating the need for high-speed testers ...
Currently, Built-In Self-Test (BIST) is the primary self-test methodology available and is widely used for testing embedded memory cores. ...
The outputs of the scan chains are compressed on-chip using a MISR. Test points may be inserted to improve the fault coverage. ...
doi:10.1145/337292.337599
dblp:conf/dac/ChenDSSC00
fatcat:m7k46u6t3ve37gn67e3bety56e
Scalable and Efficient Methods for Uncertainty Estimation and Reduction in Deep Learning
[article]
2024
arXiv
pre-print
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2024; you can also visit the original URL.
The file type is application/pdf.
estimation and reduction in deep learning, with a focus on Computation-in-Memory (CIM) using emerging resistive non-volatile memories. ...
To address the challenges of deploying NNs in resource-constrained safety-critical systems, this paper summarizes the (4th year) PhD thesis work that explores scalable and efficient methods for uncertainty ...
Furthermore, to reduce the testing overhead of large-scale NN models to an absolute minimum, we introduce the oneshot testing method that requires only a single test vector and a forward pass, as detailed ...
arXiv:2401.07145v1
fatcat:pg4eecawgzcyjf5r2ylx6wbnhm
DART: Dependable VLSI test architecture and its implementation
2012
2012 IEEE International Test Conference
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2019; you can also visit the original URL.
The file type is application/pdf.
The DART also equips a technique to improve the test coverage using the rotating test and a technique to consider the test environment such as temperature or voltage using novel ring-oscillator-based monitors ...
Although many electronic safety-related systems require very high reliability, it is becoming harder and harder to achieve it because of transient faults such as soft errors or delay-related failures, ...
Acknowledgements Many other people helped with our project, and the authors would particularly like to thank Prof. Fujiwara of Osaka Gakuin University, Dr. Uchiyama, Dr. Kanekawa and Mr. ...
doi:10.1109/test.2012.6401581
dblp:conf/itc/SatoKYHIMUHSS12
fatcat:xs4fs537tvflxfu7vnstxanree
Editorial
2018
Journal of electronic testing
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2019; you can also visit the original URL.
The file type is application/pdf.
This issue features approximate computing, analog circuit diagnosis, memory testing, system-on-chip (SoC) test scheduling, hardware security, and fault tolerance. It contains nine articles. ...
If we take advantage of relaxed requirements, we can design electronic circuits to reduce power and hardware or enhance performance. ...
This issue features approximate computing, analog circuit diagnosis, memory testing, system-on-chip (SoC) test scheduling, hardware security, and fault tolerance. It contains nine articles. ...
doi:10.1007/s10836-018-5743-8
fatcat:fpridvgrifdvdmt4mt52oj7eeq
MT-SBST: Self-test optimization in multithreaded multicore architectures
2010
2010 IEEE International Test Conference
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
In this paper, we present a novel self-test optimization strategy for multithreaded, multicore microprocessor architectures and apply it to both manufacturing testing (execution from on-chip cache memory ...
reduce the overall test execution time and on the same time to increase the overall fault coverage. ...
The SBST key idea is to exploit the instruction set architecture and on-chip programmable resources to execute effective self-test programs. ...
doi:10.1109/test.2010.5699277
dblp:conf/itc/FoutrisPGAVG10
fatcat:zmsqythtujchtoikemek7ifmbe
Weighted Random Pattern Generator by Using BIST
2015
International Journal of Science and Research (IJSR)
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2022; you can also visit the original URL.
The file type is application/pdf.
In Built-In Self-Test (BIST),test patterns are generated and applied to the circuit-under-test (CUT) by on-chip hardware; minimizing hardware overhead is a major concern of BIST implementation. ...
in power consumption and high fault coverage with minimum ****** of test patterns. ...
Introduction A System-on-Chip (SoC) increasing capacity of system integration in modern semi-conductor processes, reduced time-to-market requirements, and decreasing system costs make multi core systems ...
doi:10.21275/v4i12.nov152188
fatcat:em4efhwlwfdb7gaxjbdla4icvq
Implementation of Low Power TPG using LFSR and single input changing generator (SICG) for BIST Application: A Review
2015
IJIREEICE
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2021; you can also visit the original URL.
The file type is application/pdf.
A novel test pattern generator which is more suitable for built in self test (BIST) structures used for testing of VLSI circuits. ...
The objective of the BIST is to reduce power dissipation without affecting the fault coverage. ...
The main advantages of this method are reduction of the test data volume; require less time to test the application and its reusability for logic cores on a system-on-chip (SOC). ...
doi:10.17148/ijireeice.2015.3429
fatcat:36upg5ss4rfwvltaxo4cgvo2xa
Design and Development of a Modified AXI Based BIST Technique for Memory Architectures
2019
International journal of recent technology and engineering
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2019; you can also visit the original URL.
The file type is application/pdf.
Built In Self Test (BIST) is a hardware memory test architecture deployed in many System on Chip devices to enable fault detection. ...
This technique reduces the cost and time needed to test the memory systems. Different BIST modules need to be used to detect faults in different memories. As a result, design complexity increases. ...
Built In Self Test (BIST) is a hardware memory test architecture deployed in many System on Chip devices to enable fault detection. ...
doi:10.35940/ijrte.d4446.118419
fatcat:77axnucgyjberony2vjxs5ajoq
A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores
2004
Journal of electronic testing
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2014; you can also visit the original URL.
The file type is application/pdf.
We have introduced a low-cost at-speed BIST architecture that enables conventional microprocessors and DSP cores to test their functional blocks and embedded SRAMs in system-on-a-chip architectures using ...
A test algorithm which utilizes a mixture of existing memory testing techniques and covers all important memory faults is presented in this paper. ...
Acknowledgment The authors would like to thank Professor Krishnendu Chakrabarty of ECE Department of Duke University for his useful suggestions. ...
doi:10.1023/b:jett.0000023679.08518.bf
fatcat:ps3ege2h65cojbbtfoux5opp7a
International Test Conference
1986
IEEE Design & Test of Computers
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2019; you can also visit the original URL.
The file type is application/pdf.
SUMMARY: The first session on the application of Artificial Intelligence to test concentrates on its use in the areas of test pattern generation, built-in self-test, and fault location. introduces a novel ...
"Performance Assurance of Memories
Embedded In VLSI Chips"
Two diverse methods are proposed to assure performance
characteristics of memories buried in random logic on the
same chip. ...
What are the advantages and disadvantages of each of these methods, and when is it best to use one approach over the other? ...
doi:10.1109/mdt.1986.294973
fatcat:6dlybbnmgjhqll6rte6uaisnyi
Power dissipation, variations and nanoscale CMOS design: Test challenges and self-calibration/self-repair solutions
2007
2007 IEEE International Test Conference
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
In this paper, we provide an overview of major low-power and variation-tolerant design techniques; discuss related test issues and focus on effectiveness of self-calibration/self-repair solutions to maintain ...
Low-power and process-tolerant designs, however, impose new test challenges and may even have conflicting requirements for test -affecting delay fault coverage, I DDQ testability, parametric yield, and ...
Novel DFT circuits can help in reducing the test time without affecting fault coverage. One such technique, referred as double sensing, is applied to test the read stability of SRAM cells. ...
doi:10.1109/test.2007.4437659
dblp:conf/itc/BhuniaR07
fatcat:bdsfonjkkrhnxeigu3gog4y6de
2001 technology roadmap for semiconductors
2002
Computer
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2014; you can also visit the original URL.
The file type is application/pdf.
Acknowledgments We acknowledge the efforts of the many individuals who contributed to making the 2001 edition of The International Technology Roadmap for Semiconductors a successful endeavor. ...
Test will continue to leverage functional test methodology as one opportunity to obtain the coverage required to guarantee outgoing product quality. ...
DFTbased approaches require continued research to increase coverage of process defects by developing advanced methodologies to apply patterns based on existing fault models to designs and identifying novel ...
doi:10.1109/2.976918
fatcat:mv3q7f3l2zfjng2i5rvipkdhsi
Design and Analysis of Low Power Memory Built in Self Test Architecture for SoC based Design
2015
Indian Journal of Science and Technology
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2019; you can also visit the original URL.
The file type is application/pdf.
This paper targets on the low power design of Memory Built In Self Test (MBIST) architecture for System on Chip (SoC) based design. ...
Proposed address generator is developed with the blend of gray code counter and modulo counter. Bit reversing technique is adopted in this paper to generate the last pattern of gray code counter. ...
Built In Self Test (BIST) techniques are found to be better alternative compared to external testing as they provide on chip test pattern generation and response analysis. ...
doi:10.17485/ijst/2015/v8i14/62716
fatcat:4y4zflqee5byvmiwrkd4huyw64
« Previous
Showing results 1 — 15 out of 8,689 results