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Low power network processor design using clock gating
2005
Proceedings. 42nd Design Automation Conference, 2005.
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We propose to monitor the average number of idle threads in a time window, and gate off the clock network of unused PEs when a subset of PEs is enough to handle the network traffic. ...
Network processors (NPs) have emerged as successful platforms to providing both high performance and flexibility in building powerful routers. ...
In section 2, we introduce the network processor model that is used in our design. ...
doi:10.1109/dac.2005.193904
fatcat:otmvejgzjva3djqbk74wlvqcpa
Low power network processor design using clock gating
2005
Proceedings of the 42nd annual conference on Design automation - DAC '05
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We propose to monitor the average number of idle threads in a time window, and gate off the clock network of unused PEs when a subset of PEs is enough to handle the network traffic. ...
Network processors (NPs) have emerged as successful platforms to providing both high performance and flexibility in building powerful routers. ...
In section 2, we introduce the network processor model that is used in our design. ...
doi:10.1145/1065579.1065766
dblp:conf/dac/LuoYYB05
fatcat:5ald3js4nbamzcpmnflhupsoky
Dynamic Power Optimization of 32 Bit MIPS Processor Using Clock Gating For Low Power Applications
2019
International journal of recent technology and engineering
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Clock gating and data gating method is adopted in this paper and to reduce dynamic power. This design is implemented on 28nm kintex-7 FPGA Board and power is analyzed ...
The demand for low power processor is increasing day by day in mobile application for video, audio, mixed signal processing, gaming console and battery-operated electronic devices. ...
AND gate combined with latch is called Integrated Clock Gate (ICG) [5] . Ultra low power design this data driven gating is used to reduce the area. . ...
doi:10.35940/ijrte.b3575.078219
fatcat:i6puxsgf5bduxpdc7yyhm7wdxm
BTI-Gater: An Aging-Resilient Clock Gating Methodology
2014
IEEE Journal on Emerging and Selected Topics in Circuits and Systems
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Results on commercial processors show that BTI-Gater can effectively reduce N/PBTI-induced clock skew of up to 17ps, which can be converted to up to 19.7% leakage power saving compared to pure design guardbanding ...
Two Integrated Clock Gating (ICG) cell circuits are proposed to alternate clock idle state between logic high and logic low for each clock gating operation. ...
Clock Gating Use Cases Clock gating is one of the most popular power management techniques, due to its low reaction latency and small implementation overhead. ...
doi:10.1109/jetcas.2014.2315882
fatcat:5kixja26g5aopek3xbw5kuxirm
Energy characterization of a tiled architecture processor with on-chip networks
2003
Proceedings of the 2003 international symposium on Low power electronics and design - ISLPED '03
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Tiled architectures provide a paradigm for designers to turn silicon resources into processors with burgeoning quantities of programmable functional units and memories. ...
This design selectively turns on and off 48 SRAM macros, 96 functional unit clusters, 32 fetch units, and over 250 unique processor pipeline stages, all according to the needs of the computation and environment ...
Figure 3 : 3 Energy Cost of Dynamic Network Messages
Figure 5 : 5 Speedup versus 1 tile
Figure 7 7 Figure 7: Energy w/ Hypothetical Tile-level Clock-gating Adding tile-level clock gating to the processor ...
doi:10.1145/871506.871610
dblp:conf/islped/KimTMW03
fatcat:razng76qqrbr7gchmtc2ps5vgu
Energy characterization of a tiled architecture processor with on-chip networks
2003
Proceedings of the 2003 international symposium on Low power electronics and design - ISLPED '03
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Tiled architectures provide a paradigm for designers to turn silicon resources into processors with burgeoning quantities of programmable functional units and memories. ...
This design selectively turns on and off 48 SRAM macros, 96 functional unit clusters, 32 fetch units, and over 250 unique processor pipeline stages, all according to the needs of the computation and environment ...
Figure 3 : 3 Energy Cost of Dynamic Network Messages
Figure 5 : 5 Speedup versus 1 tile
Figure 7 7 Figure 7: Energy w/ Hypothetical Tile-level Clock-gating Adding tile-level clock gating to the processor ...
doi:10.1145/871604.871610
fatcat:ahiamwcidferje4spayz2jeneq
Low Power Design for ASIC Cores
2001
VLSI design (Print)
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Different low power design techniques are used, including dual voltage, low power library elements, accurate power reporting, pseudomicrocode, transition-once logic, clock gating, and others. ...
A semicustom ASIC design methodology is used to develop a low power DSP core for mobile (battery powered) applications. ...
Low power clock splitters are used exclusively to drive low power latches and enable clock gating. ...
doi:10.1155/2001/90464
fatcat:dwffghzuxzbqnpsej6ekahv3qa
A gate level sensor network for integrated circuits temperature monitoring
2010
2010 IEEE Sensors
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The sensor network consists of a set of simple gates, which are superimposed over the actual design of any IC. ...
Since the delay of gates is proportional to their temperature, we can obtain temperature of the network gates, by measuring the delay of the gates in the self-sensing network. ...
We introduce the concept of using simple networks of gates with a small number of simple gates (e.g. smallest, fastest, and the lowest power gateinverter) to obtain information about speed change at a ...
doi:10.1109/icsens.2010.5690094
fatcat:ybosbvlzijav7pdrtwzy2me2ju
Exploring sparsity of firing activities and clock gating for energy-efficient recurrent spiking neural processors
2017
2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)
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Our LSM processor leverage the sparsity of firing activities to allow for efficient event-driven processing and activity-dependent clock gating. ...
As a model of recurrent spiking neural networks, the Liquid State Machine (LSM) offers a powerful brain-inspired computing platform for pattern recognition and machine learning applications. ...
On FPGAs, dedicated routing resources are typically used to ensure the low-skew clock signal delivery across a fairly large design. ...
doi:10.1109/islped.2017.8009197
dblp:conf/islped/LiuJL17
fatcat:p7o6jiz5y5dt7b5lmtrf7nb7dm
A 167-Processor Computational Platform in 65 nm CMOS
2009
IEEE Journal of Solid-State Circuits
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All processors and shared memories are clocked by local fully independent, dynamically haltable, digitally-programmable oscillators and are interconnected by a configurable circuit-switched network which ...
A 167-processor computational platform consists of an array of simple programmable processors capable of per-processor dynamic supply voltage and clock frequency scaling, three algorithm-specific processors ...
An AND gate is used to determine when all PMOS power gates have been switched off. ...
doi:10.1109/jssc.2009.2013772
fatcat:rskm7pf2fbaxdpj2tko4hvuxti
Low power methodology and design techniques for processor design
1998
Proceedings of the 1998 international symposium on Low power electronics and design - ISLPED '98
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IBM's ASIC design methodologies is used to develop a low power microprocessor for the mobile (battery powered) marketplace. ...
The design called for a reduction of active power by a factor of 10 times from an estimate of a product designed in a standard 3 volt ASIC design system. ...
Low power clock splitters are used exclusively to match low power latches and enable clock gating. ...
doi:10.1145/280756.280931
dblp:conf/islped/BrennanDKV98
fatcat:ic7vgmgcyfcmnpy43qi666b4oa
The Complete Switching Circuit Design for CPU Joint Body Biasing and Supply Voltage Scaling
2019
Zanco Journal of Pure and Applied Sciences
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This paper presents a complete design of a switching network for joint body biasing and supply voltage scaling (VBB-VDD), which is consistent in allowing compact low power consumption and low temperatures ...
in the core of high-performance processors. ...
This switch configuration is called a transmission gate. Using transmission gate as a switch, the schematic diagram of the switching network is modified as shown in Fig. 2 . ...
doi:10.21271/zjpas.31.s3.3
fatcat:gbi2oy4tajfq7in76ggw2n2gzi
Low Power Gated-Clock Design for Multi-core DSP Based SDR Platform
2016
International Journal of u- and e- Service, Science and Technology
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Experiments show that the proposed low power gated-clock architecture can provide effective low-power performance for multi-core DSP in SDR platforms. ...
Research has focused on low-power design in SDR platform since the SDR platform is sensitive to power consumption. ...
Meanwhile, the proposed gated-clock low power design method can cooperate with other low-power techniques for achieving lower power. ...
doi:10.14257/ijunesst.2016.9.6.16
fatcat:uenx346qwbfftfsdu5imhxcu7e
Novel nonvolatile memory hierarchies to realize "normally-off mobile processors"
2014
2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)
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•To realize N-off processor ver.1, advanced STT-MRAM, normally-off type memory cell design, ultra-fast power gating are three key points. ...
Energy consumed (%) General STT-MRAM Active power Increases drastically! Standby power is low, but active energy is extremely higher than that of SRAM even using conventional STT-MRAM. ...
doi:10.1109/aspdac.2014.6742851
dblp:conf/aspdac/FujitaNNTA14
fatcat:xk552w6e5fdu3hovblcn24cf2a
Spike-driven gated recurrent neural network processor for electrocardiogram arrhythmias detection realised in 55-nm CMOS technology
2020
Electronics Letters
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In this Letter, an asynchronous spike-driven processor based on gated recurrent neural network algorithm for electrocardiogram (ECG) cardiac arrhythmias detection has been designed. ...
Based on the processor, the proposed ECG detection model, containing a many-tomany gated recurrent unit layer and a fully connected layer, can achieve a high classification overall accuracy of 97.8% using ...
.: 'Real-time ultra-low power ECG anomaly detection using an event-driven neuromorphic processor', IEEE Trans. Biomed. ...
doi:10.1049/el.2020.2224
fatcat:z7szybasxbcq7fkhzgdqrbrmzu
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