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Cost effective FPGA probabilistic fault emulation
2014
2014 NORCHIP
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This paper presents a cost effective FPGA fault emulation technique for probabilistic errors. ...
For this purpose, the emulated fault injection (EFI) components proposed are a trade-off between the desire for speed/performance and the inherent physical device limitations of the FPGA. ...
ACKNOWLEDGMENT This work has been supported by the Seventh Framework Program of European Union under Grant Agreement 309129, project i-Risc. ...
doi:10.1109/norchip.2014.7004710
dblp:conf/norchip/BoncaloASP14
fatcat:fvcvstm6kjg5tkkgxrgfxmk6yu
Probability aware fault-injection approach for SER estimation
2018
2018 IEEE 19th Latin-American Test Symposium (LATS)
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This approach enables the use of just one PRNG and a decoder for the entire device, instead of a pair 'PRNGcomparator' per element, leading to a significant reduction in logic blocks consumption. ...
On the other hand, studies in the stochastic computing domain deal with a probabilistic faultinjection approach. ...
The fault distribution is applied to the circuit under test (CUT) using an autonomous emulated fault-injection environment. ...
doi:10.1109/latw.2018.8349692
dblp:conf/latw/ArmelinNd18a
fatcat:phr73o4dfvdahc7oxlshcm4gum
A confidence-driven model for error-resilient computing
2011
2011 Design, Automation & Test in Europe
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The performance and cost of the computing model are estimated using a 45 nm CMOS technology and the functionality is verified by FPGA-based emulation. ...
The confidencedriven computing model adapts to the fluctuating error rates at the device substrate level to guarantee the reliability of computation at the system level. ...
ACKLOWEDGEMENT The authors would like to thank Farhana Sheikh, Keith Bowman, Feng Xue, Tanay Karnik, Chris Ramming and Shekhar Borkar for guidance and suggestions. ...
doi:10.1109/date.2011.5763255
dblp:conf/date/ChenKZBSNS11
fatcat:yp3dxqw4frhszfn7tu3vejzua4
Design and Evaluation of Confidence-Driven Error-Resilient Systems
2014
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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The EC technique improves the system reliability by more than four orders of magnitude when errors are of short duration. ...
Deeply scaled CMOS circuits are increasingly susceptible to transient faults and soft errors; emerging post-CMOS devices can be more vulnerable, sometimes exhibiting erratic errors of arbitrary duration ...
ACKNOWLEDGMENT The authors would like to thank Y. Kim for help implementing the CDC model and H. Naeimi, S. Sandhu, F. Sheikh, and K. Bowman for suggestions. ...
doi:10.1109/tvlsi.2013.2277351
fatcat:ni37vig4i5eozcd4kbyu7ymcxu
An FPGA-based framework for run-time injection and analysis of soft errors in microprocessors
2011
2011 IEEE 17th International On-Line Testing Symposium
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State-of-the-art nanoscale manufacturing technologies are more vulnerable to soft errors. ...
While the framework is applicable to arbitrary software, we demonstrate its usage by characterizing soft errors effects on several software filters used in aviation for probabilistic sensor data fusion ...
[20] discuss various types of fault injection techniques for medium-size non-programmable circuits. ...
doi:10.1109/iolts.2011.5993836
dblp:conf/iolts/SauerTMLSPBB11
fatcat:zunt7c7mobd47frs2hrmtjcjry
Fault tolerant design for low power hierarchical search motion estimation algorithms
2011
2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip
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Furthermore, a 1.8 dB improvement in PSNR under the same energy savings of 70% for both algorithms is shown establishing the superior resilience of the proposed algorithm to probabilistic computing over ...
With the fault tolerant algorithm design (MC-TSS) proposed in this paper, we show that energy savings that can be realized with probabilistic computing increase to 70% versus 57% with the conventional ...
We use a different noise model that emulates hardware faults such as false bit flipping due to thermal noise possible in future CMOS technology nodes. ...
doi:10.1109/vlsisoc.2011.6081649
dblp:conf/vlsi/DhootMCC11
fatcat:57kg33x7i5g4nm4orzgtczffba
Interval-Valued Reduced Ensemble Learning Based Fault Detection and Diagnosis Techniques for Uncertain Grid-Connected PV Systems
2022
IEEE Access
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One of the most promising renewable energy technologies is photovoltaics (PV). ...
Next, in order to more improve the diagnosis abilities, two interval kernel PCA (IKPCA)-based EL classifiers are developed. ...
A first fault F 1 was emulated by introducing an open-circuit fault on one of the inverter switches at the time (inverter fault). ...
doi:10.1109/access.2022.3167147
fatcat:piaxojui2bf6jpliagy7nsc6s4
Variability Expeditions: A Retrospective
2019
IEEE design & test
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The research showed that some of the classical fault tolerance techniques had outlived utility in the new computing systems. ...
As we built circuits, microarchitecture, devised coding methods, and adaptive algorithms, the research accelerated the trends toward fault tolerance in programming languages from fringe efforts such as ...
The research showed that some of the classical fault tolerance techniques had outlived utility in the new computing systems. ...
doi:10.1109/mdat.2018.2889103
fatcat:4yskrdyganh6baxctvjaekccya
Robust Sequential Circuits Design Technique for Low Voltage and High Noise Scenarios
2016
MATEC Web of Conferences
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In this paper we introduce an innovative input and output data redundancy principle for sequential block circuits, the responsible to keep the state of the system, showing its efficiency in front of other ...
All electronic processing components in future deep nanotechnologies will exhibit high noise level and/or low S/N ratios because of the extreme voltage reduction and the nearly erratic nature of such devices ...
Acknowledgments This research work has been supported by the Spanish Ministry of Science and Innovation (MICINN) through projects TEC2008-01856 and PLE2009-0024, and Government of Mexico under grant 164013 ...
doi:10.1051/matecconf/20164202003
fatcat:5xlku5cz6bg55i5jhr6euyjq2a
Integration of nanoscale memristor synapses in neuromorphic computing architectures
2013
Nanotechnology
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circuit which represents a radical departure from conventional neuro-computing approaches, as it uses memristors to directly emulate the biophysics and temporal dynamics of real synapses. ...
block for implementing brain-inspired probabilistic computing paradigms that are robust to variability and fault-tolerant by design. ...
Acknowledgment This work was supported by the European CHIST-ERA program, via the "Plasticity in NEUral Memristive Architectures" (PNEUMA) project. ...
doi:10.1088/0957-4484/24/38/384010
pmid:23999381
fatcat:6isdvp5f4vhgddskpmlx2xq5ra
Validation of the Proposed Hardness Analysis Technique for FPGA Designs to Improve Reliability and Fault-Tolerance
2018
International Journal of Advanced Computer Science and Applications
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Reliability and fault tolerance of FPGA systems is a major concern nowadays. The continuous increase of the system's complexity makes the reliability evaluation extremely difficult and costly. ...
, which improves reliability. ...
fault simulation and emulation of designs. ...
doi:10.14569/ijacsa.2018.091201
fatcat:ghd7nf4wojehhdnt7hwsy2avjq
Analysis of Min-Sum based decoders implemented on noisy hardware
2013
2013 Asilomar Conference on Signals, Systems and Computers
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Motivated by the problem of designing fault-tolerant memories built out from unreliable components, this paper investigates the performance of two noisy Min-Sum-based decoders on Binary Symmetric Channels ...
We also present the finite length performance of two Min-Sum based decoders, and point out the excellent performance of the noisy Self-Corrected Min-Sum decoder, which exhibits almost the same performance ...
The objective of the SCMS is to determine if a correction circuit "plugged into" the noisy MS decoder can improve the robustness of the decoder to hardware noise. ...
doi:10.1109/acssc.2013.6810411
dblp:conf/acssc/NgassaSD13
fatcat:bwe6wlawljfjppzu2qtw3ck33i
An FPGA-based real quantum computer emulator
2018
Journal of Computational Electronics
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This paper describes a proposition of a universal and scalable quantum computer emulator, in which the FPGA hardware emulates the behavior of a real quantum system, capable of running quantum algorithms ...
The article also shows the proposed quantum emulator architecture, exposing a standard programming interface, and working results of an implementation of an exemplary quantum algorithm. ...
There are many proposed emulator architectures based on FPGA circuits, but none of them are fully focused on simple, naturally parallel emulation of quantum circuits. ...
doi:10.1007/s10825-018-1287-5
fatcat:rnijfqnnxzfozkjecbyvbdvkce
Time-Multiplexed Online Checking: A Feasibility Study
2008
2008 17th Asian Test Symposium
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This incurs less area overhead, and could maintain fault coverage similar to traditional checkers. The test quality is studied using a probabilistic model. ...
The implementation feasibility using a Field-Programmable Gate Array (FPGA) is demonstrated. ...
Acknowledgements The authors acknowledge the valuable suggestions from Professor Jin-Fu Li at the National Central University, Taiwan ...
doi:10.1109/ats.2008.23
dblp:conf/ats/GaoCLC08
fatcat:77cwgr26evf4veobfcijq5r2ey
On the use of inexact, pruned hardware in atmospheric modelling
2014
Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences
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Peter Düben performed the numerical simulations, developed the emulator for pruned hardware and wrote large parts of the paper. ...
The idea to write a paper on the use of pruned hardware in Lorenz '96 developed during a meeting of Peter Düben, Hugh McNamara, Krishna Palem and Tim Palmer. ...
The significance value quantifies the impact of a node on the accuracy of the circuit. ...
doi:10.1098/rsta.2013.0276
pmid:24842031
pmcid:PMC4024232
fatcat:f6an3ch2gnabxawszkb5mjpfoi
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