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A Reconfigurable High Speed Dedicated BISR Scheme for Repair Intra Cell Faults in Memories
2017
International Journal of Trend in Scientific Research and Development
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Future version of Re-BISR contains a programmable MBIST scheme to accommodate several March algorithms and also include virtual blocks for redundant memories to increase the repair rate. ...
Re-BISR can repair the faults of several memories in an IC and thus has lesser hardware overhead compared to a dedicated BISR scheme where each RAM has a dedicated BISR module. ...
Therefore, the time efficient and area efficient BISR scheme is needed to improve the yield and performance of RAMs in SOC's economically. ...
doi:10.31142/ijtsrd7054
fatcat:qqullzska5ej7cwae4gfraiola
A Fast Built-in Redundancy Analysis for Memories With Optimal Repair Rate Using a Line-Based Search Tree
2009
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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The proposed BIRA analyzes redundancies quickly and efficiently with optimal repair rate by using a selected fail count comparison algorithm. ...
Index Terms-Built-in self-repair (BISR), built-in self-test (BIST), redundancy analysis (RA), yield improvement. ...
ACKNOWLEDGMENT The authors would like to thank all members of Computer Systems and the Reliable SOC Laboratory from Yonsei University, Seoul, Korea, for their insightful feedback and comments on drafts ...
doi:10.1109/tvlsi.2008.2005988
fatcat:a4zifjxxzfe3tftyi4ivjnnl7i
A Proposed RAISIN for BISR for RAM's with 2D Redundancy
unpublished
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The proposed word oriented memory test methodology for Built-In Self-Repair (BISR) Scheme with 2D Redundancy for High Repair Efficiency (HRE). ...
This allows to use RAMS, e.g. from memory generators, without spare rows and spare columns as used in classic redundancy concepts. ...
By reusing the bitmap for the RA to serve spare bits in normal mode, the HRE-BISR scheme can enhance the RR. ...
fatcat:nqxp7femh5az3ddvdewg6mcs24
Infrastructures and Algorithms for Testable and Dependable Systems-on-a-Chip
[article]
2003
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[34, 43, 46, 25] analyze algorithms that optimize the repair solution for a given bit failure pattern in a redundant RAM. ...
This paragraph proposes an innovative architecture for SRAMs, characterized by BISR capabilities based on Cell-only redundant space allocation at the user level. ...
Although, the RAM core has not been explicitly designed to cover faults located in the BISR logic, the module was able to repair the 92.7% of the faults inserted in the BISR Controller and the 89.16% of ...
doi:10.6092/polito/porto/2709266
fatcat:zulzplxkhnbyjdpentdj77z2hy
Testability features of the alpha 21364 microprocessor
International Test Conference, 2003. Proceedings. ITC 2003.
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Abstract This paper describes an optimized DFT architecture and its implementation strategy for an Intel high performance (>3 GHz) microprocessor. ...
Major DFT features and ATPG techniques implemented are described and key results are presented to show the return-on-investments (ROI) in the high volume manufacturing (HVM) test environments. ...
Acknowledgement The authors would like to recognize the significant contributions provided by the PX microprocessor DFX team and the PX architecture and design teams throughout the entire project. ...
doi:10.1109/test.2003.1270906
dblp:conf/itc/ErlangerBD03
fatcat:htpwv6m7f5fzzn3yq7bmo7m3um