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Hierarchical Modeling, Optimization, and Synthesis for System-Level Analog and RF Designs
2007
Proceedings of the IEEE
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| The paper describes the recent state of the art in hierarchical analog synthesis, with a strong emphasis on associated techniques for computer-aided model generation and optimization. ...
We then survey recent ideas in hierarchical synthesis for analog systems and focus in particular on numerical techniques for handling the large number of degrees of freedom in these designs and for exploring ...
McConaghy, who have contributed largely to the work on hierarchical synthesis and performance modeling. ...
doi:10.1109/jproc.2006.889371
fatcat:nsxteyaqpzfl5no5v5iboedrgy
A formal approach for high level synthesis of linear analog systems
2006
Proceedings of the 16th ACM Great Lakes symposium on VLSI - GLSVLSI '06
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This paper proposes a novel high level synthesis methodology for optimal linear analog systems in a formal and systematic way. ...
The methodology defines an abstract description of the system, selects an optimal architecture by exploring the entire architecture space and finally performs a behavioral sizing of the architecture. ...
In this paper, we present an original method for systematically and automatically generating optimal architecture for linear analog systems. ...
doi:10.1145/1127908.1127987
dblp:conf/glvlsi/PanditMP06
fatcat:b6ix7adptnck7no4lzjft5b7xm
Deterministic approaches to analog performance space exploration (PSE)
2005
Proceedings of the 42nd annual conference on Design automation - DAC '05
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One approximates the feasible performance space based on linearized circuit models and is suitable for investigating a large number of performances. ...
Performance space exploration (PSE) determines the range of feasible performance values of a circuit block for a given topology and technology. ...
This mixed behavioral-transistor level modeling of analog systems leads to a hierarchical design process, where system specifications are propagated top-down from the behavioral level to the transistor ...
doi:10.1145/1065579.1065807
dblp:conf/dac/MuellerSGS05
fatcat:4fyoelkjl5dzbkjaelsrobofri
Deterministic approaches to analog performance space exploration (PSE)
2005
Proceedings. 42nd Design Automation Conference, 2005.
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One approximates the feasible performance space based on linearized circuit models and is suitable for investigating a large number of performances. ...
Performance space exploration (PSE) determines the range of feasible performance values of a circuit block for a given topology and technology. ...
This mixed behavioral-transistor level modeling of analog systems leads to a hierarchical design process, where system specifications are propagated top-down from the behavioral level to the transistor ...
doi:10.1109/dac.2005.193937
fatcat:juqdxiqugjh7beuz3ajkenzgvy
Exploration-based high-level synthesis of linear analog systems operating at low/medium frequencies
2003
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a methodology for high-level synthesis of continuous-time linear analog systems. ...
Experiments showed that linear analog systems operating at low/medium frequencies (like telecommunication systems and filters) can be synthesized in a reasonably long time and with reduced effort. ...
ACKNOWLEDGMENT The authors would like to thank the Associate Editor and the anonymous reviewers for their very useful comments and suggestions that have helped improve this paper. ...
doi:10.1109/tcad.2003.818374
fatcat:43nbr635izcndnoqmgst265gpu
A Decomposition-Based Symbolic Analysis Method for Analog Synthesis from Behavioral Specifications
[chapter]
2000
IFIP Advances in Information and Communication Technology
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This paper discusscs a technique for symbolic analysis of largc analog systems. The method exploits the hierarchical structure and uniformity of a system for producing compact symbolie expressions. ...
The discLlssed technique is useful for synthesis, inside an exploration-Ioop, as it avoids repeatedly computing the symbolic models. ...
An Analog Performance Tree (APT) describes the computational path for calculating linear (linearized) attributes of an SFG. ...
doi:10.1007/978-0-387-35498-9_27
fatcat:zz6wnf2mcvetvo7443uv743yba
Performance space modeling for hierarchical synthesis of analog integrated circuits
2005
Proceedings of the 42nd annual conference on Design automation - DAC '05
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The complexity of typical analog SoC subsystems however calls for efficient methods that can handle design hierarchy, in terms of both performance estimation and hierarchical design optimization method ...
Automated analog sizing is becoming an unavoidable solution for increasing analog design productivity. ...
An analog designer just has to choose a solution at the system level according to the performance specs, and immediately all the design variables of the complete system are set. ...
doi:10.1145/1065579.1065809
dblp:conf/dac/GielenME05
fatcat:ryybvix2fnepdnxaza4oo36odm
Performance space modeling for hierarchical synthesis of analog integrated circuits
2005
Proceedings. 42nd Design Automation Conference, 2005.
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The complexity of typical analog SoC subsystems however calls for efficient methods that can handle design hierarchy, in terms of both performance estimation and hierarchical design optimization method ...
Automated analog sizing is becoming an unavoidable solution for increasing analog design productivity. ...
An analog designer just has to choose a solution at the system level according to the performance specs, and immediately all the design variables of the complete system are set. ...
doi:10.1109/dac.2005.193939
fatcat:ydek45wp6rh2xfz73h3jgaz5ya
Yield-aware hierarchical optimization of large analog integrated circuits
2008
2008 IEEE/ACM International Conference on Computer-Aided Design
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Hierarchical optimization using building circuit block pareto performance models is an efficient and well established approach for optimizing the nominal performances of large analog circuits. ...
Our approach extends the efficiency of hierarchical analog optimization, enjoyed for improving nominal circuit performances, to yield-aware optimization. ...
Hierarchical Optimization in Nominal Case In hierarchical optimization, a large analog system is decomposed into several building blocks. ...
doi:10.1109/iccad.2008.4681555
dblp:conf/iccad/YuL08
fatcat:z5kv3yk375eyfpqwf33mae5jqq
Synthesis tools for mixed-signal ICs
1996
Proceedings of the 33rd annual conference on Design automation conference - DAC '96
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In this tutorial, we look at the last decade's worth of progress on analog circuit synthesis and layout tools. We focus on the frontend and backend of analog and mixed-signal IC design flows. ...
Digital synthesis tools such as logic synthesis and semicustom layout have dramatically changed both the frontend (specification to netlist) and backend (netlist to mask) steps of the digital IC design ...
Leuven for their assistance with the preparation of this manuscript. The authors at CMU were supported by the Semiconductor Research Corp, U.S. National Science Foundation, IBM, Intel and Harris. ...
doi:10.1145/240518.240573
dblp:conf/dac/CarleyGRS96
fatcat:is5p3o2he5dbpeqnh5djuf5gta
Design tool solutions for mixed-signal/RF circuit design in CMOS nanometer technologies
2007
2007 Asia and South Pacific Design Automation Conference
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This invited paper describes progress in modeling techniques for design and verification of complex integrated systems, in circuit and yield optimization tools for analog/RF circuits, as well as in signal ...
The scaling of CMOS technology into the nanometer era enables the fabrication of highly integrated systems, which increasingly contain analog and/or RF parts. ...
Analog synthesis consists of two major steps: (1) circuit synthesis followed by (2) layout synthesis. ...
doi:10.1109/aspdac.2007.358024
dblp:conf/aspdac/Gielen07
fatcat:nmg3jf2h7zbyxe5joafirfz724
Hierarchical constraint transformation using directed interval search for analog system synthesis
1999
Proceedings of the conference on Design, automation and test in Europe - DATE '99
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In this paper, we present a hierarchical approach for constraint transformation. ...
intervals that assists the search engine and an analog p erformance estimator. ...
Arsintescu et al 3 address the problem of AC constraint transformation for a class of linear continuous-time circuits using hierarchical parameter modeling and constrained optimization techniques. ...
doi:10.1145/307418.307517
fatcat:vrziitwmcvaupevbpcygryggja
State-of-the-Art on Analog Layout Automation
[chapter]
2016
Analog Integrated Circuit Design Automation
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In the past few years, several tools for the automation of the analog integrated circuit (IC) cell and system layout design, with application on both new and reused designs have emerged. ...
layout generation tools, and the recent advances in layout-aware analog synthesis approaches. ...
Interesting features for hierarchical symmetry and hierarchical proximity groups that often appear in analog circuits. ...
doi:10.1007/978-3-319-34060-9_2
fatcat:7flyp6nwd5aprexg2ccab4abau
State of the Art on Analog Layout Automation
[chapter]
2012
SpringerBriefs in Applied Sciences and Technology
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In the past few years, several tools for the automation of the analog integrated circuit (IC) cell and system layout design, with application on both new and reused designs have emerged. ...
layout generation tools, and the recent advances in layout-aware analog synthesis approaches. ...
Interesting features for hierarchical symmetry and hierarchical proximity groups that often appear in analog circuits. ...
doi:10.1007/978-3-642-33146-6_2
fatcat:miizfmqdqbd67azo7hb3j72xna
Technology mapping and retargeting for field-programmable analog arrays
2000
Proceedings of the conference on Design, automation and test in Europe - DATE '00
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Rapid prototyping followed by technology retargeting provides a fast and cost-effective approach to analog system synthesis. ...
A novel structural approach based on hierarchical pattern matching and covering is employed to map the analog behavior onto the FPAA. ...
Acknowledgments: The authors would like to thank Adrian Nunez, Nagu Dhanwada and Alex Doboli of the VASE team, and special thanks to Satish Ganesan. ...
doi:10.1145/343647.343700
fatcat:fxpp23va5vawhpkhwnh3fqsm2m
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