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Figures-of-Merit to Evaluate the Significance of Switching Noise in Analog Circuits
2015
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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An analysis flow is proposed to determine the significance of induced (switching) noise in analog circuits. The proposed flow is exemplified through two commonly used amplifier topologies. ...
Furthermore, time-domain switching noise amplitude (at the bulk node) at which the input device and switching noise magnitude are equal (in the frequency domain) is determined as the second figure-of-merit ...
CONCLUSION An analysis flow has been proposed to evaluate the significance of switching noise in analog circuits. ...
doi:10.1109/tvlsi.2014.2386315
fatcat:mm5dbfacqnbbjaufs3xgccrs5y
Adaptive Sub-Threshold Voltage Level Control for Voltage Deviate-Domino Circuits
2023
Intelligent Automation and Soft Computing
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Positive Channel Metal Oxide Semiconductor (PMOS) has been replaced by Negative Channel Metal Oxide Semiconductor (NMOS) in recent years, with low dimension-switching changes in order to shape the mirror ...
In this study regarding Adaptive Sub Threshold Voltage Level Control Problem, the researchers intend to solve the contention issues, reduce power dissipation, and increase the noise immunity by proposing ...
Funding Statement: The authors received no specific funding for this study.
Conflicts of Interest: The authors declare that they have no conflicts of interest to report regarding the present study. ...
doi:10.32604/iasc.2023.028758
fatcat:7jkryx2a5zdlbopve3bawkk5vm
CMOS circuits for Gb/s serial data communication
1995
IBM Journal of Research and Development
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The following sections discuss the custom design approaches used to implement these functions, beginning with the analog circuits used in clock recovery and synthesis, and followed by simple, but high-speed ...
These factors lead to lower system cost, provided that the analog circuits can be combined with the digital logic without requiring a unique technology to achieve the required performance. ...
(EWEN at WATSON He has been associated with a variety of hardware projects as an analog and digital circuit designer, logic designer, and lead engineer. ...
doi:10.1147/rd.391.0073
fatcat:kxb3z5on4ncx7ieehstmki72c4
Low-Power Successive Approximation ADC with 0.5 V Supply for Medical Implantable Devices
2013
CVR Journal of Science & Technology
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figure of merit 0.14pJ/Conversion. ...
In this paper the design and implementation of very low-power Analog to Digital converter, which is used in medical implantable devices like pacemakers et al. ...
Figure. The figure 5. shows the operation of the comparator circuit. There are two operation phases, reset phase and regeneration or evaluation phase. ...
doi:10.32377/cvrjst0411
fatcat:7qessbos4nbq7blt5ds2kpmlyy
A 1.8-V digital-audio sigma-delta modulator in 0.8-μm CMOS
1997
IEEE Journal of Solid-State Circuits
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Oversampling techniques based on sigma-delta (Σ∆) modulation offer numerous advantages for the realization of high-resolution analog-to-digital (A/D) converters in a low-voltage environment. ...
The experimental modulator has been designed with fully-differential switched-capacitor integrators employing different input and output common-mode levels and boosted clock drivers in order to facilitate ...
Vincent for facilitating fabrication of the prototype circuits at Rockwell International. Special thanks are also due to Dr. M. Loinaz, Dr. B. Razavi, S. Sidiropoulos, and Dr. D. ...
doi:10.1109/4.585245
fatcat:aaj7kh77vfhpjduho4rec2f4du
A 10b 100MS/s 4.5mW pipelined ADC with a time sharing technique
2010
2010 IEEE International Solid-State Circuits Conference - (ISSCC)
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To reduce the power consumption, the front-end sample-and-hold (S/H) circuit is removed because the S/H dissipates significant power and contributes additional noise that degrades SNR. ...
However, in this work, MADC2 and MDAC3 stages have identical evaluation time in order to keep the same level of complexity and power consumption of the clock generation circuit. ...
Acknowledgement: This work was supported by Mediatek, and the authors would like to thank TSMC for the support in chip fabrication. ...
doi:10.1109/isscc.2010.5433927
dblp:conf/isscc/HuangL10
fatcat:2vrnxwknwjgdzdmmdbnoobnm7a
A 2.1 μW/channel current-mode integrated neural recording interface
2016
2016 IEEE-EMBS International Conference on Biomedical and Health Informatics (BHI)
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The integrated interface circuit is realized in a 65 nm CMOS technology, and consumes less than 2.1 μW/channel of which A/D converter consumes 367 nW, corresponding to a figure of merit of 14 fJ/conv. ...
In this paper, we present a neural recording interface circuit for biomedical implantable devices, which includes low-noise signal amplification, band-pass filtering, and current-mode successive approximation ...
367 nW, corresponding to a figure of merit of 14 fJ/conv. ...
doi:10.1109/bhi.2016.7455945
dblp:conf/bhi/ZjajoL16a
fatcat:2zea3zbjpbbmtowgfsj3mnq33i
Optimization of Delta-Sigma ADC for Column-Level Data Conversion in CMOS Image Sensors
2007
Instrumentation and Measurement Technology Conference (IMTC), Proceedings, IEEE
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The decimator is also optimized by placing part of the circuit at the chip level. Zero distortion is possible in the decimator due to the discrete-time nature of the input signal. ...
For a 0.18µm process, the design achieves 80dB of signal-to-noise ratio (SNR), including a 10dB margin for kTC noise not simulated, and consumes 210µW of power at a 50kHz sampling rate. ...
ACKNOWLEDGEMENTS The authors gratefully acknowledge the support of the Natural Sciences and Engineering Research Council of Canada. ...
doi:10.1109/imtc.2007.379253
fatcat:kdh2qhku6je25nxqdo23jgkfdq
A Power Scalable and Low Power Pipelined ADC
[chapter]
2010
Pipelined ADC Design and Enhancement Techniques
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A 10-bit pipeline Analog-to-Digital Converter (ADC) is designed such that its average power is scaleable with sampling rate over a large variation of sampling rates. ...
Next I am tremendously indebted to the aid and friendship of the 'Master's crew', of Navid, Rob, and Trevor who in addition to helping me develop and refine my skills as a mixed-signal designer, have made ...
was adjusted to achieve an optimal figure of merit. ...
doi:10.1007/978-90-481-8652-5_7
fatcat:2s7yeyvqonhrpdvhxqseowxwl4
Analysis and optimization of substrate noise coupling in single-chip RF transceiver design
2002
Computer-Aided Design (ICCAD), IEEE International Conference on
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The relentless move toward single chip integration of RF, analog and digital blocks results in significant noise coupling effects that can degrade performance and hence, should be controlled. ...
The integration of the methodology in a typical RF design flow is illustrated and its successful application to achieve a singlechip integration of a transceiver demonstrated. ...
ACKNOWLEDGEMENT The authors would like to thank N. Joehl, P.Favre and C. Dehollain for helpful discussions and for providing the test circuits. ...
doi:10.1145/774572.774619
dblp:conf/iccad/KoukabBD02
fatcat:mofdxlikabdk3bfori37r6rwdu
Jitter in ring oscillators
1997
IEEE Journal of Solid-State Circuits
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This figure of merit is used to relate fundamental circuit-level noise sources (such as thermal and shot noise) to system-level jitter performance. ...
A major contribution is the identification of a design figure of merit , which is independent of the number of stages in the ring. ...
ACKNOWLEDGMENT The efforts of L. DeVito, A. Gusinov, R. Croughwell, B. Surette, and T. Freitas are greatly appreciated. ...
doi:10.1109/4.585289
fatcat:2zi6venkizbnbcxtobkd2ze6lu
Low-Phase-Noise CMOS Relaxation Oscillators for On-Chip Timing of IoT Sensing Platforms
2022
Electronics
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Electrical simulations performed on a 0.18 μm CMOS design confirmed that the proposed technique effectively rejects the flicker component of the comparator noise, allowing for a 152 dBc/Hz figure of merit ...
The design of low-phase-noise fully integrated frequency references is often a critical aspect in the development of low-cost integrated circuits for communication interfaces, sensing platforms, and biomedical ...
to the output noise in switched-capacitor (SC) circuits [14] . ...
doi:10.3390/electronics11111794
fatcat:wolz5hk75bfvxdi5rcku2yunju
Jitter in Ring Oscillators
[chapter]
2009
Phase-Locking in High-Performance Systems
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This figure of merit is used to relate fundamental circuit-level noise sources (such as thermal and shot noise) to system-level jitter performance. ...
A major contribution is the identification of a design figure of merit , which is independent of the number of stages in the ring. ...
ACKNOWLEDGMENT The efforts of L. DeVito, A. Gusinov, R. Croughwell, B. Surette, and T. Freitas are greatly appreciated. ...
doi:10.1109/9780470545492.ch24
fatcat:uw5xu6tpwnb4nowedm3z7fgx5q
A Design of Low-Power 10-bit 1-MS/s Asynchronous SAR ADC for DSRC Application
2020
Electronics
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The proposed architecture achieves a figure of merit (FOM) of 17.4 fJ/conversion, signal-to-noise distortion ratio (SNDR) of 60.39 dB, and an effective number of bits (ENOB) of 9.74 bits with a sampling ...
To improve the linearity of the digital-to-analog converter (DAC) and energy efficiency, a common mode-based monotonic charge recovery (CMMC) switching technique is proposed. ...
Conflicts of Interest: The authors declare no conflict of interest. ...
doi:10.3390/electronics9071100
fatcat:f5mpykb66vfhrl2bicsie32us4
Considerations for Cost-Efficient Calibration of Scaled ADCs
[chapter]
2011
Analog Circuit Design
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The increasing use of digitally enhanced ADC architectures proves to be the main driver for the observed improvement in area and power with scaling. ...
Trade-off analysis between mismatch compensation in the analog domain (digitally assisted trimming, possibly in combination with up-scaling) vs. the digital domain (digital post-distortion) is required ...
Figure 4 : 4 Fraction of ADC architectures published in ISSCC and VLSI in different calendar years.
Figure 5 : 5 Power figure-of-merit vs. area figure-of-merit (FOM). ...
doi:10.1007/978-94-007-1926-2_5
fatcat:bbwi5iq7f5exlllmrmsbh763ri
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