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Technique based on On-Chip Current Sensors and Neighbourhood Comparison Logic to detect resistive-open defects in SRAMs
2013
2013 14th Latin American Test Workshop - LATW
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The main idea behind the hardware-based technique is to explore the evaluation throughout an analysis of the current of neighbouring SRAM cells in order to identify the presence of manufacturing defects ...
In this context, a technique based on On-Chip Current Sensors (OCCS) and Neighbourhood Comparison Logic (NCL) to detect resistive-open defects in SRAMs is proposed. ...
The NCL adopted in this work aims at reducing the overhead related to area and power consumption, since they represent important concerns in VDSM technologies. ...
doi:10.1109/latw.2013.6562688
dblp:conf/latw/LavrattiBCVM13
fatcat:wzze3gyd2ndnzdv3s26t44p5rq
Temperature Aware Methodology for Low Power SoC System
2016
International Journal of Advanced Science and Technology
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In this paper, we explore the tradeoff between thermal and interconnect energy when allocating tasks in MPSoC and to devlop an efficient system. ...
Energy consumption is a major concern in many embedded computing systems. Several studies have shown that cache memories account for about 50% of the total energy consumed in these systems. ...
between the total chip power and the local power budget value is computed. ...
doi:10.14257/ijast.2016.90.01
fatcat:vb3msyjxirdkldqu25xx5hxi4e
Power-based Side Channel Analysis and Fault Injection: Hacking Techniques and Combined Countermeasure
2021
International Journal of Advanced Computer Science and Applications
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Hence, the majority of these secured approaches are used for precise and single attack and it is difficult to thwart hybrid attack, such as combined power and fault attacks. ...
In this work, the Advanced Encryption Standard is used as a case study in order to analyse the most well-known physical-based Hacking techniques: Differential Fault Analysis (DFA) and Correlation Power ...
Power consumption-based SCA uses a leakage model in order to define a relationship between the device power consumption and the secret information employed. ...
doi:10.14569/ijacsa.2021.0120583
fatcat:3rgsgj7nf5eqxdhjfwf6xpa6wu
Reliability-aware dynamic energy management in dependable embedded real-time systems
2010
ACM Transactions on Embedded Computing Systems
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Therefore, there is an interesting trade-off between system reliability and energy consumption ]. ...
the sensitive region in a semiconductor device. ...
The relation between fault rate and voltage scaling was explored and hardware error detection and correction schemes have been proposed [Ernst et al. 2004 ]. ...
doi:10.1145/1880050.1880062
fatcat:bqm4zvja4zhs3n5pkg37bp5xfa
Janus: An uncertain cache architecture to cope with side channel attacks
2017
2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)
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2017 pre-print arXiv:1710.09039v1 fatcat:ja7r3xzbbvdhxkluqwls3xlw6e
Attackers collect and analyze timing behavior, I/O data, or power consumption in these systems to undermine their effectiveness in protecting sensitive information. ...
The new secure processor architecture has minimal hardware overhead and significant improvement in protecting against power analysis and timing behavior attacks. ...
In SPA attacks, the power consumption graphs related to the electrical activities of the IC modules are interpreted visually. ...
doi:10.1109/mwscas.2017.8053051
dblp:conf/mwscas/HosseinzadehIDP17
fatcat:x3ebjfmp4rbtdoku3r2lgno4x4
Novel transient-fault detection circuit featuring enhanced bulk built-in current sensor with low-power sleep-mode
2012
Microelectronics and reliability
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The proposed circuit was optimized in terms of power consumption and enhanced with low-power sleep-mode. In addition, a calibration method for bulk built-in current sensors is presented. ...
This work presents a novel circuit for detecting transient faults in combinational and sequential logic. ...
of detecting a minimum transient-fault profile (section 4); An extensive transistor-level simulation-based exploration of the BBICS size limits in function of their response times and power consumptions ...
doi:10.1016/j.microrel.2012.06.149
fatcat:6cntt5j7dza2fksqvufh42mf3y
Winograd Convolution: A Perspective from Fault Tolerance
[article]
2022
arXiv
pre-print
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Then, we explore the use of fault tolerance of winograd convolution for either fault-tolerant or energy-efficient NN processing. ...
Other than the computing efficiency, we observe its great potential in improving NN fault tolerance and evaluate its fault tolerance comprehensively for the first time. ...
, and reduce power consumption according to [42] . ...
arXiv:2202.08675v1
fatcat:clnipyq3sbbstkez2kbkdrmtlq
DYNAMIC VOLTAGE AND FREQUENCY SCALING IN FAULT TOLERANT REAL-TIME SYSTEMS
2016
Facta Universitatis Series Automatic Control and Robotics
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In this paper, we analyze the faults tolerance capability of hard real-time systems under power consumption constraints. ...
We proposea heuristic-based algorithm to find processor frequencies at which each real-time task should be executed so that: 1) the power consumption does not exceed the upper power limit; 2) the fault ...
algorithm to maximize the faulttolerance under power consumption constraint.The algorithm can be used in the early stages of RTS design process as a tool for rapidly exploring the tradeoff between the ...
doi:10.22190/fuacr.v15i3.1786
fatcat:wuwyef3hzrhofmfao76dy7homi
DYNAMIC VOLTAGE AND FREQUENCY SCALING IN FAULT TOLERANT REAL-TIME SYSTEMS
2016
Facta Universitatis Series Automatic Control and Robotics
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In this paper, we analyze the faults tolerance capability of hard real-time systems under power consumption constraints. ...
We proposea heuristic-based algorithm to find processor frequencies at which each real-time task should be executed so that: 1) the power consumption does not exceed the upper power limit; 2) the fault ...
algorithm to maximize the faulttolerance under power consumption constraint.The algorithm can be used in the early stages of RTS design process as a tool for rapidly exploring the tradeoff between the ...
doi:10.22190/fuacr1603227d
fatcat:tv4jovhxfzckxel3wd2gobvwli
Tuning synthesis flags to optimize implementation goals: Performance and robustness of the LEON3 processor as a case study
2018
Journal of Parallel and Distributed Computing
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The steady growth in complexity of FPGAs have led designers to rely more and more on manufacturers' and third parties' design tools to meet their implementation goals. ...
Resulting configurations are implemented to estimate the actual impact, and statistical significance, of each considered synthesis flag. ...
Acknowledgements This work has been partially funded by the Ministerio de Economía, Industria y Competitividad de España under grant agreement no TIN2016-81075-R, and the "Programa de Ayudas de Investigación ...
doi:10.1016/j.jpdc.2017.10.002
fatcat:f7y2yjqsybelhm2gm3qwgkidqm
Exploring subsets of standard cell libraries to exploit natural fault masking capabilities for reliable logic
2007
Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI - GLSVLSI '07
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We compare how subset libraries effect the trade-offs between reliability, area, power, and performance. Further, we show that added benefits of reduced cell library size can benefit the design. ...
To address this, we demonstrate how exploiting the natural fault masking characteristics of logical functions can be achieved by exploring the design space for selecting subsets of cells from within a ...
Additionally, the reduction in cells has been shown to increase the efficiency of the synthesis tools and increase the speed, area and power consumption for logic blocks [15] . ...
doi:10.1145/1228784.1228838
dblp:conf/glvlsi/NessHL07
fatcat:l3mt4vfikvbnlgisiqsn5kzfx4
On the potential of significance-driven execution for energy-aware HPC
2014
Computer Science - Research and Development
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The objective is to reduce energy consumption by using NTV and avoid the cost of fault-tolerant mechanisms. ...
[11] suggest that power savings between 10× and 50× are possible with NTV, albeit with a 5× to 10× reduction in clock frequency. ...
doi:10.1007/s00450-014-0265-9
fatcat:g7uf3gpqsfekzgwcns3gmrwhwi
Evaluation of a Network-on-Chip designed to deal with multiple processors in a nanosatellite
2020
Revista Brasileira de Computação Aplicada
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Results of lower silicon consumption, concomitant to economies in design and reduction of sensitivity to cosmic ionization, can be observed after the elaborated experiments. ...
They usually have between four and five boards with embedded electronics, which control all their functions. ...
, and adopted mechanisms to deal with faults; Section 4 introduces experimental results related to the network latency, and Section 5 introduces the silicon consumption for the proposed network; Section ...
doi:10.5335/rbca.v12i2.10120
fatcat:uqmelkcmqvex5muaicby52xeom
Understanding Power Consumption and Reliability of High-Bandwidth Memory with Voltage Underscaling
[article]
2020
arXiv
pre-print
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We explore and characterize the rate and types of these reduced-voltage-induced bit flips and present a fault map that enables the possibility of a three-factor trade-off among power, memory capacity, ...
and fault rate. ...
This work has received financial support, in part, from Tetramax for the LV-EmbeDL project. This work is supported in part by funding from SRC and gifts from Intel, Microsoft and VMware to Onur Mutlu. ...
arXiv:2101.00969v1
fatcat:sc6ls7kii5hz3fv5xszeqkmkqq
Power consumption profile analysis for security attack simulation in smart cards at high abstraction level
2005
Proceedings of the 5th ACM international conference on Embedded software - EMSOFT '05
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Therefore, the power consumption profile is analyzed at this level. ...
As they store and deal with confidential and secret data many attacks are performed on these cards to reveal this private information. Consequently, the security demands on smart cards are very high. ...
This is important to set fast and easy countermeasures related to the power profile like instruction reordering or the insertion of dummy instructions. ...
doi:10.1145/1086228.1086268
dblp:conf/emsoft/RothbartNSWRM05
fatcat:llvehbvbrzc63ejv2zjjkkwrxa
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