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Error Mitigation Using Approximate Logic Circuits: A Comparison of Probabilistic and Evolutionary Approaches
2016
IEEE Transactions on Reliability
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However, generating an optimal redundant logic circuit that is able to mask the faults with the highest probability while minimizing the area overheads is a challenging problem. ...
The probabilistic approach approximates a circuit in a greedy manner based on a probabilistic estimation of the error. ...
The probablilistic approach uses a greedy algorithm based on line approximations and dynamic error probability estimations. ...
doi:10.1109/tr.2016.2604918
fatcat:wg3skzzk4vfpdoslr7hqucvb6i
An approximated soft error analysis technique for gate-level designs
2014
IEICE Electronics Express
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Related studies have mainly focused on the soft error rate analysis of both combinational and sequential logic circuits, which includes techniques for dynamic simulation, and pathbased statistical estimation ...
We employ node conditional probability to calculate the logical propagation probabilities without using static probability. ...
If to a certain degree, the requirement for this type of analysis agrees with the estimation errors, one can apply an approximated but fast method to the SET analysis. ...
doi:10.1587/elex.11.20140224
fatcat:oka3pgldnndavfayqrj422p3sa
Probabilistic Error Modeling for Nano-Domain Logic Circuits
2009
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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We estimate the overall output error probability by comparing the outputs of a dynamic error-encoded model with an ideal logic model. ...
We demonstrate the efficiency and accuracy of these approximate inference schemes by comparing estimated results with logic simulation results. ...
Two errors occurring simultaneously will mask each other due to logic masking. ...
doi:10.1109/tvlsi.2008.2003167
fatcat:olf4rx6z5fbfdbxqc7kyghhdxe
Approximate Triple Modular Redundancy: A Survey
2020
IEEE Access
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Cartesian genetic programming and dynamic probability estimation have also been used for obtaining approximate modules of ATMR. ...
APPROXIMATE-COMPUTING-BASED TMR Reference [13] introduced the use of approximate logic circuits for TMR by using testability estimations. ...
doi:10.1109/access.2020.3012673
fatcat:annw3bcktfbrdetlwhyv7te6wy
Fast and Accurate SER Estimation for Large Combinational Blocks in Early Stages of the Design
2018
IEEE Transactions on Sustainable Computing
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In the core of the framework lies MASkIt, a novel approach that combines signal probabilities with technology characterization to swiftly compute the logical, electrical, and timing masking effects of ...
Soft Error Rate (SER) estimation is an important challenge for integrated circuits because of the increased vulnerability brought by technology scaling. ...
Using primary input signals, error probabilities and gate error probabilities, the reliability of the circuit is computed in linear-time complexity with the number of gates of the circuit. ...
doi:10.1109/tsusc.2018.2886640
fatcat:3tdtepbvdrgypel7y3ghglijzy
Gate sizing to radiation harden combinational logic
2006
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Gates are hardened to single-event upsets (SEUs) with specified worst case characteristics in increasing order of their logical masking probability, thereby maximizing the reduction in the soft error failure ...
The asymmetry in the logical masking probabilities at a gate is leveraged by decoupling the physical from the logical (Boolean) aspects of soft error susceptibility of the gate. ...
There is a significant correlation between gates with low electrical masking probability and gates with low logical masking probability. ...
doi:10.1109/tcad.2005.853696
fatcat:gbv77mfsbbaepefynw2qtb76u4
Soft Error Rates with Inertial and Logical Masking
2009
2009 22nd International Conference on VLSI Design
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We find that for some circuits with many levels of logic there exists a critical single event transient (SET) width. ...
We analyze the neutron induced soft error rate (SER). An induced error pulse is modeled by two parameters, probability of occurrence and probability density function of the pulse width. ...
[2] present a soft error rate estimation technique based on error probability propagation. ...
doi:10.1109/vlsi.design.2009.77
dblp:conf/vlsid/WangA09
fatcat:xyyiyk4jabaspapbsl6e4xyese
Soft Error Rate Estimation in Deep Sub-micron CMOS
2007
13th Pacific Rim International Symposium on Dependable Computing (PRDC 2007)
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This simple relationship will simplify the task of estimating circuit-level Soft Error Rate (SER) and support the development of an efficient SER modeling and optimization tool that might eventually be ...
Soft errors resulting from the impact of charged particles are emerging as a major issue in the design of reliable circuits at deep sub-micron dimensions. ...
Further, they may use a broad range of circuit styles, including dynamic and/or domino logic as well as a variety of latch styles. ...
doi:10.1109/prdc.2007.34
dblp:conf/prdc/ZengB07
fatcat:wp7yyylfefcxbfj5srn4c27v5q
Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits
[chapter]
2008
Design, Automation, and Test in Europe
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The first part of this paper presents a tool for accurate soft-error tolerance analysis of nanometer circuits (ASERTA) that can be used to estimate the soft-error tolerance of nanometer circuits consisting ...
The second part of the paper presents a tool for soft-error tolerance optimization of nanometer circuits (SERTOPT) using the tolerance estimates generated by ASERTA. ...
Also note that isj is an approximation to the actual probability value since in circuits with reconvergent fan-out, the probability that gate s is sensitized to gate i conditions the probability of gate ...
doi:10.1007/978-1-4020-6488-3_28
fatcat:p2tbwgbfvnalnaux7ua3rdoziy
Soft-Spot Analysis: Targeting Compound Noise Effects in Nanometer Circuits
2005
IEEE Design & Test of Computers
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In dynamic logic, the affecting factors differ from those in static circuits. ...
If such information isn't available, assuming that logic 1 and 0 have equal probabilities at all PIs is a good approximation. ...
doi:10.1109/mdt.2005.95
fatcat:hhqczvrf5rhn7mwklobk6woqbe
Analysis of the Impact of Electrical and Timing Masking on Soft Error Rate Estimation in VLSI Circuits
2022
Technologies
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An accurate SER evaluation is provided based on a SPICE-oriented electrical masking analysis, combined with a TCAD characterization process. ...
Thus, to design radiation-hardened and reliable ICs, the Soft Error Rate (SER) estimation constitutes an essential procedure. ...
However, in [6] a simple ramp approximation equation is used to estimate the SET pulse width at the gate output. ...
doi:10.3390/technologies10010023
fatcat:kmapbtnoe5ayxoi2p7yyq7eu44
SoftArch: an architecture-level tool for modeling and analyzing soft errors
2005
2005 International Conference on Dependable Systems and Networks (DSN'05)
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Our results are consistent with, but more comprehensive than, prior work, and motivate selective and dynamic architecture-level soft error protection mechanisms. ...
Recent work has motivated architecture-level studies of soft errors since the architecture can mask many raw errors and architectural solutions can exploit workload knowledge. ...
probability that, given correct inputs, the result produced by the corresponding circuit at the end of the computation is incorrect because of soft errors. e logic can be estimated using circuit level ...
doi:10.1109/dsn.2005.88
dblp:conf/dsn/LiABR05
fatcat:n7zhrmy7djdixhsytn4mu6ajii
Characterizing System-Level Masking Effects against Soft Errors
2021
Electronics
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The remainder are also masked by several software-level masking effects, such as dynamically dead instructions, compare and logical instructions that do not change the result, and incorrect control flows ...
Further analyses showed that 71% of soft errors are overwritten by write operations before being used, and the CPU does not use 20% of soft errors at all after fault injections. ...
Randomly chosen 1000 faults can represent the population with 99% confidence level and 5% error margin based on probability theory [31] . ...
doi:10.3390/electronics10182286
fatcat:ipsnsk6aizgw7mxiqsf4ugc7bm
Impact of Logic Synthesis on Soft Error Rate of Digital Integrated Circuits
2012
2012 IEEE Computer Society Annual Symposium on VLSI
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masking can be evaluated using the error propagation probability (EPP), the likelihood that an error in one component propagates to output of the circuit. ...
Determining Input Probabilities Using probabilistic graph models to estimate error propagation probability requires knowledge of signal probability for each node. ...
doi:10.1109/isvlsi.2012.67
dblp:conf/isvlsi/Limbrick12
fatcat:6lgrqdpl3veipka3od2vcw5iva
MARS-C: modeling and reduction of soft errors in combinational circuits
2006
Proceedings - Design Automation Conference
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The framework can be used for selective gate sizing targeting radiation hardening which is done only for gates with error impact exceeding a certain threshold. ...
The results obtained with the proposed symbolic framework are within 7% average error and up to 5000X speedup when compared to HSPICE detailed circuit simulation. ...
PAPER CONTRIBUTION In order to estimate the probability of errors in combinational logic, our symbolic tool uses Binary Decision Diagrams (BDDs) and Algebraic Decision Diagrams (ADDs). ...
doi:10.1109/dac.2006.229323
fatcat:mbehz4zi2fajtiekda4dzzf6gq
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