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Low power LDPC decoder with efficient stopping scheme for undecodable blocks
2011
2011 IEEE International Symposium of Circuits and Systems (ISCAS)
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An efficient technique for early detection of undecodable blocks during LDPC decoding is introduced. ...
Index Terms-early termination, undecodable blocks, full parallel, LDPC, low power, energy efficiency, 10GBASE-T, 65 nm CMOS ...
The proposed stopping methods in [3] , [4] monitor the convergence of mean magnitude of variable nodes and check nodes, respectively. ...
doi:10.1109/iscas.2011.5937929
dblp:conf/iscas/MohseninSB11
fatcat:wkoj7xcwenf2nakzopves65g5y
A new LDPC decoding algorithm aided by segmented cyclic redundancy checks for magnetic recording channels
2005
IEEE transactions on magnetics
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Moreover, the CRC is also used for an early stopping criterion of LDPC decoding. Simulation results verify our claims. ...
The key idea is that the messages from the variable nodes with correct checksum are fixed to deterministic log likelihood ratio values during LDPC iterative decoding. ...
LDPC DECODING BASED ON MULTIPLE CRCS
A. CRC-Aided LDPC Decoding Algorithm The proposed decoding algorithm is based on the iterative belief propagation (IBP) decoding in [3] . ...
doi:10.1109/tmag.2005.851861
fatcat:cbgzkz34dfbhfpqyfkjjjxegr4
Power Reduction Techniques for LDPC Decoders
2008
IEEE Journal of Solid-State Circuits
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Second, we propose an efficient method to detect early convergence of the iterative decoder and terminate the computations, thereby reducing dynamic power. ...
This paper investigates VLSI architectures for lowdensity parity-check (LDPC) decoders amenable to low-voltage and low-power operation. ...
ACKNOWLEDGMENT The authors would like to thank the editors and reviewers of IEEE TRANSACTIONS ON VLSI SYSTEMS for their valuable comments in the initial stages of this submission. ...
doi:10.1109/jssc.2008.925402
fatcat:snzpqiar6fbgrk7buivznwdzuy
Decoding of Decode and Forward (DF) Relay Protocol using Min-Sum Based Low Density Parity Check (LDPC) System
2018
International Journal of Communication Networks and Information Security
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This paper reviews existing methods for the min-sum based LDPC decoding system as the low complexity decoding system. ...
Check Node (VCN) operation methods that have the potential to be used in DF relay protocol. ...
The aim of this paper is to review the literature on the minsum based LDPC decoding method for decode and forward (DF) relay protocol and describe the current methods available in the min-sum based LDPC ...
dblp:journals/ijcnis/SuudZOH18
fatcat:pfyuflfsbvedrda5po3ith3pim
A 100 Gbps LDPC Decoder for the IEEE 802.11ay Standard
2018
Zenodo
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The goal of the work is to design a standard compliant LDPC decoder for 802.11ay with high throughput, high energy and area efficiency. ...
on the 802.11ad standard. ...
Methods A full row-based layered LDPC decoder with frame interleaved schedule is proposed for 802.11ay, implemented in 16 nm FinFET as well as 28 nm CMOS. ...
doi:10.5281/zenodo.2567762
fatcat:n4gv7bc2e5duzeqjspvmksqwqe
Adaptive deactivation and zero-forcing scheme for low-complexity LDPC decoders
2017
EURASIP Journal on Wireless Communications and Networking
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threshold-based node deactivation for variable nodes and zero-forcing scheme for check nodes remarkably reduce decoding complexity required for similar error performance. ...
A modified message propagation algorithm is proposed for a low-complexity decoder of low-density parity-check (LDPC) codes, which controls the information propagated from variable and check nodes.The proposed ...
supported by the MSIP (Ministry of Science, ICT and Future Planning), Korea, under the ITRC (Information Technology Research Center) support program (IITP-2017-2015-0-00385) supervised by the IITP (Institute for ...
doi:10.1186/s13638-017-0934-z
fatcat:rmnyxgprljdudpgwxoiin5vlzm
An 8.29 mm$^{2}$ 52 mW Multi-Mode LDPC Decoder Design for Mobile WiMAX System in 0.13 $\mu$m CMOS Process
2008
IEEE Journal of Solid-State Circuits
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Based on overlapped decoding mechanism, the decoding latency can be reduced to 68.75% of nonoverlapped method, and the hardware utilization ratio can be enhanced from 50% to 75%. ...
This paper presents a multi-mode decoder design for Quasi-Cyclic LDPC codes for Mobile WiMAX system. ...
In addition, the regularity in structure-based method can provide more help on the decoder design. ...
doi:10.1109/jssc.2008.916606
fatcat:id4bvykhw5cenm3uy4cqxfbxyi
A 5.79-Gb/s Energy-Efficient Multirate LDPC Codec Chip for IEEE 802.15.3c Applications
2012
IEEE Journal of Solid-State Circuits
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Index Terms-IEEE 802.15.3c, low-density parity-check (LDPC) codes, row-based layered scheduling. ...
After implemented in 65-nm 1P10M CMOS process, the proposed LDPC decoder chip can achieve maximum 5.79-Gb/s throughput with the hardware efficiency of 3.7 Gb/s mm and energy efficiency of 62.4 pJ/b, respectively ...
ACKNOWLEDGMENT The authors would like to thank National Chip Implement Center (CIC), Taiwan, and United Microelectronics Corporation (UMC), Taiwan, for technology support. ...
doi:10.1109/jssc.2012.2194176
fatcat:fpnbpkar2fcdbl4kgo3m7tergu
An Early Termination Criterion for Stochastic LDPC Decoding
2016
Lecture Notes on Information Theory
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Stochastic decoding is an excellent approach for Low-Density Parity-Check (LDPC) codes which are adopted in many communication standards, including 10GBASE-T, DVB-S2, WiMAX. ...
Then, an early termination criterion is proposed as an efficient way to speed up the decoding procedure. ...
In one iteration, belief messages are passed from the variable nodes to the check nodes along the interconnected edges, and then returned from the check nodes to the variable nodes. ...
doi:10.18178/lnit.4.1.7-12
fatcat:j5eyh35nxrcfzo6zo3yzd3zcl4
Trends and challenges in LDPC hardware decoders
2009
2009 Conference Record of the Forty-Third Asilomar Conference on Signals, Systems and Computers
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This paper provides an overview of current research in LDPC decoder algorithms and architectures that are well suited for hardware implementations. ...
While there has been much research on LDPC decoders and their VLSI implementations, many difficulties to achieve requirements remain such as lower error floors, reduced interconnect complexities, smaller ...
The recent proposed post-processing methods perform a message biasing scheme [25] on check nodes or bit flipping on selective variable nodes [24] . ...
doi:10.1109/acssc.2009.5469947
fatcat:lqyd7x4txfginm3qcfehqz4vhm
Parallel LDPC decoder implementation on GPU based on unbalanced memory coalescing
2012
2012 IEEE International Conference on Communications (ICC)
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In this paper, a new algorithm is proposed that enables coalesced memory access in both the read and write operations for one half of the decoding process -either the bit-tocheck or the check-to-bit message ...
Overall, experimental results show that proposed GPU-based LDPC decoder achieves more than 234x-speedup compared to CPU-based LDPC decoders and also outperforms existing GPU-based decoders by a significant ...
CONCLUSION Flexible LDPC decoder implementation based on GPU is gaining popularity. In this paper, methods for parallel implementation of an LDPC decoder on GPU were presented. ...
doi:10.1109/icc.2012.6363991
dblp:conf/icc/KangM12
fatcat:vnl3a23xk5ehlhi7eq75psxbb4
Power Consumption of LDPC Decoders in Software Radio
[article]
2011
arXiv
pre-print
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The prosperity of software radio has motivated us to investigate the implementation of LDPC decoders on processors. ...
In this paper, we estimate and compare complexity and power consumption of LDPC decoding algorithms running on general purpose processors. ...
That motivates the need of an efficient method to estimate energy consumption when the early stopping mechanism is applied. ...
arXiv:1103.5128v1
fatcat:p3adxpxuzzfw7fq3wp7a7y6oqi
Reliability Ratio Weighted Bit Flipping– Sum Product Algorithm for Regular LDPC Codes
2022
Digital Signal Processing and Artificial Intelligence for Automatic Learning
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In this paper, a new algorithm called Reliability Ratio Weighted Bit Flipping-Sum Product (RRWBFSP) decoding is proposed for low-density parity-check codes. ...
The results of the simulation show that the new algorithm achieves a 0.34 dB performance gain over of the standard Sum-Product decoding algorithms. ...
Decoding Complexity The complexity of decoding LDPC codes is evaluated based on the number of operations, such as multiplication, division and Table 1 . ...
doi:10.6025/dspaial/2022/1/1/28-36
fatcat:pcqlkeg2zjedxjxa7ysnbcjwvq
A flexible NoC-based LDPC code decoder implementation and bandwidth reduction methods
2011
Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP)
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1 A Flexible NoC-based LDPC code decoder implementation and bandwidth reduction methods Carlo Condo, Guido Masera, Senior Member IEEE Abstract-The need for efficient and flexible LDPC (Low Density parity ...
MESSAGE STOPPING WITH THRESHOLD T HR ON LDPC DECODER WITH Px PES, AND Smsg STOPPED MESSAGES. T gain IS THE THROUGHPUT GAIN OVER THE AVERAGE. ...
doi:10.1109/dasip.2011.6136889
dblp:conf/dasip/CondoM11
fatcat:vu7dlghxxnd4ned3zzdqtdwjam
A Survey on Trapping Sets and Stopping Sets
[article]
2017
arXiv
pre-print
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This survey examines trapping sets and stopping sets in LDPC codes over channels such as BSC, BEC and AWGNC. ...
LDPC codes are used in many applications, however, their error correcting capabilities are limited by the presence of stopping sets and trapping sets. ...
before submission, Dr Dhammika Jayalath for his help with the decoding simulations over AWGNC, and Xuan He for his suggestions on how to present our BER data. ...
arXiv:1705.05996v1
fatcat:dr2utwphurehfkecmucprwucgq
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