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Architecture level optimization of 3-dimensional tree-based FPGA
2014
Microelectronics Journal
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The ability of the design flow to decide a horizontal or vertical network break-point based on design specifications is a defining feature of our design methodology. ...
segregating the logic blocks and programmable interconnect resources into multiple tiers to build a 3D stacked Tree-based FPGA. ...
The optimized routing resources and TSV count are listed in Table 3 . In Mesh-based industrial 3D FPGA, the same power is used for individual blocks in multiple tiers of 3D chip. ...
doi:10.1016/j.mejo.2013.12.011
fatcat:sxyjcy3cwnd57kainxzd3txdc4
A Review of the Design Challenges for the 3-D on Chip Network Paradigms
2017
International Journal of Computer Applications
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Multiple design issues have to be addressed in this respect such as high chip temperature due to increasing power density leading to large interconnect-delays, lack of design methodologies, large area ...
The next challenge in front of researchers in the domain of NoC is to use NoC architecture as the backbone of the upcoming generation of 3D chips. ...
One of the problems being researched in this domain is the modeling of multi-TSV arrangement in a 3-D system and their time-domain co-simulation [7] . ...
doi:10.5120/ijca2017914875
fatcat:c7wzcnumq5ca3evxthiourc66m
Physical Design Issues in 3-D Integrated Technologies
[chapter]
2010
IFIP Advances in Information and Communication Technology
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Design techniques for three-dimensional (3-D) ICs considerably lag the significant strides achieved in 3-D manufacturing technologies. ...
The techniques described in this chapter address important physical design issues and fundamental interconnect structures in the 3-D design process. ...
On-chip networks differ from traditional interconnection networks in that communication among the network elements is implemented through the on-chip routing layers rather than the metal tracks of the ...
doi:10.1007/978-3-642-12267-5_1
fatcat:hos3g3qv65bwnh36on45szlu5a
Three-dimensional Integrated Circuits: Design, EDA, and Architecture
2011
Foundations and Trends® in Electronic Design Automation
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In this article, we first give a brief introduction on the 3D integration technology, and then review the EDA challenges and solutions that can enable the adoption of 3D ICs, and finally present design ...
Design 141 Acknowledgements 142 References 143 3D Integration Technology The 3D integration technologies [2, 3] can be classified into one of the two following categories. (1) Monolithic approach. ...
[18] proposed a 3D chip multiprocessor design using network-in-memory topology. ...
doi:10.1561/1000000016
fatcat:usmthkco4rfavmnlvvmmgxolcq
Yield-aware time-efficient testing and self-fixing design for TSV-based 3D ICs
2012
17th Asia and South Pacific Design Automation Conference
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The average TSV cluster testing and selffixing time is about 3-16 testing cycle depending on the initial TSV yield. 1 ...
The Build-in-Self-Test (BIST) design with TSV redundancy scheme can help improve the system yield for today's imperfect TSV fabrication process. ...
As a result, we focus on TSV clustering design in this work. The testing circuit configuration of an N × N TSV cluster is illustrated in Figure 3 . ...
doi:10.1109/aspdac.2012.6165053
dblp:conf/aspdac/XieWX12
fatcat:bfrpdmupgfazbcmmtyiuhjcara
Virtualization Based Efficient TSV Repair for 3-D Integrated Circuits
2019
IEEE Access
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Adding redundant TSVs for repairing the faulty ones has commonly been proposed to improve the yield of TSV-based 3-D ICs. ...
Through Silicon Via (TSV) based 3-D ICs would suffer from low yield due to the faults in TSVs. In addition, TSVs introduce stress and noise in the substrate. ...
Another popular repair technique, among 2-D approaches, is a network-on-a-chip (NoC) type architecture proposed in [16] , in which the faulty TSVs are repaired using the redundant TSVs that are farther ...
doi:10.1109/access.2019.2940211
fatcat:76mab2l2cjhmtdnydhvmg6kfii
A Survey on the Security of Wired, Wireless, and 3D Network-on-Chips
2021
IEEE Access
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The main idea of on-chip networks is sharing resources to boost resource utilization, i.e., a number of on-chip components are interconnected via a shared network that is governed by a set of structural ...
To achieve this goal, the network stack (shown in Figure 1 ) is widely used in the design of on-chip networks. ...
This task is more complicated in tiny resource-constrained devices [130] such as NoC IPs. ...
doi:10.1109/access.2021.3100540
fatcat:fi3uboiwlvhzpottpgrep5nqvq
A Stackable LTE Chip for Cost-effective 3D Systems
2012
IPSJ Transactions on System LSI Design Methodology
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To address the problem of prohibitive cost of advanced fabrication technologies, one solution consists in reusing masks to address a wide range of ICs. ...
This could be achieved by a modular circuit that can be stacked to build TSV-based 3D systems with processing performance adapted to several applications. ...
In order to separate the die cost model and the 3D stacking cost model, we assume TSV-last approach is used in 3-D IC fabrication process. ...
doi:10.2197/ipsjtsldm.5.2
fatcat:5idq2zkfqjdpjdhzmcrb6xwwbu
Test and Design-for-Testability Solutions for 3D Integrated Circuits
2014
IPSJ Transactions on System LSI Design Methodology
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Test techniques and design-for-testability (DfT) solutions for 3D ICs are now being studied in the research community, and experts in industry have identified a number of hard problems related to the lack ...
of die wrappers, test scheduling, and access to dies and inter-die interconnects; (iii) interconnect testing in interposer-based 2.5D ICs; (iv) fault diagnosis and TSV repair; (v) cost modeling and test-flow ...
Resistances on the other TSVs in the network are simulated with a Gaussian distribution in which 3-σ is a 20% spread from the nominal value of 1 Ω. ...
doi:10.2197/ipsjtsldm.7.56
fatcat:56jqb2gwcne5flmqg3gt27ttbm
Test and debug solutions for 3D-stacked integrated circuits
2015
2015 IEEE International Test Conference (ITC)
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In this dissertation, we focus on TSV test prior to die bonding, as access to TSVs is limited at this stage. We propose a non-invasive method for pre-bond TSV test that does iv ...
One example is the effect of thermo-mechanical stress due to TSV fabrication process on the surrounding logic gates. ...
However, r D also depends on the design. ...
doi:10.1109/test.2015.7342421
dblp:conf/itc/DeutschC15a
fatcat:nzulytvjz5dn3bgqnnqw6qx4oy
Toward five-dimensional scaling: How density improves efficiency in future computers
2011
IBM Journal of Research and Development
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We address integration density in future computers based on packaging and architectural concepts of the human brain: a dense 3-D architecture for interconnects, fluid cooling, and power delivery of energetic ...
Interlayer cooled 3-D chip stacks solve the cooling bottlenecks, thereby allowing stacking of several such stacks, but are still limited by power delivery and communication. ...
Approximately 75% of interconnects are allocated to power and ground in planar integrated circuit (IC) designs. With 3-D chip stacks, even more pins will be needed for power delivery. ...
doi:10.1147/jrd.2011.2165677
fatcat:3njgmf6ewzfu7jxy7rezvftfky
Review of Bumpless Build Cube (BBCube) Using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI)
2022
Electronics
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Bumpless Build Cube (BBCube) using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI) is discussed. ...
Bumpless interconnect technology can increase the number of TSVs per chip due to the finer TSV pitch and the lower impedance of bumpless TSV interconnects. ...
Acknowledgments: This study was carried out based on the three-dimensional integration development program of the WOW Alliance at the Tokyo Institute of Technology, and the authors thank the alliance members ...
doi:10.3390/electronics11020236
fatcat:7nedgry4mfarpnxjflrabp4gbu
Trends of terascale computing Chips in the next ten years
2009
2009 IEEE 8th International Conference on ASIC
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Moreover, we envision that the multicore Network-on-Chip will become an infrastructure backbone and accumulate many other infrastructural functions such as memory, power and resource management, testing ...
This paper identifies ongoing and desirable trends to exploit the technology capacity and further Moore's law for terascale on-chip computing architectures in the next ten years. ...
MULTI-CORE NETWORK-ON-CHIP (MCNOC) In the previous section, we have discussed the four trends. ...
doi:10.1109/asicon.2009.5351607
fatcat:eebrdqmqkzf35jakxtbg4eyyle
Attaining Single-Chip, High-Performance Computing through 3D Systems with Active Cooling
2011
IEEE Micro
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Y system ¼ 1þ D A n þ A TSV À P n stack (2) Figure 3 shows the manufacturing yield and cost per 3D system for building a 64core chip using 45-nm technology. ...
First, because a 3D stacked system has a smaller footprint (that is, per-chip area), the manufacturing yield is higher, reducing the overall design cost. 2, 3 The on-chip interconnects are shorter in ...
doi:10.1109/mm.2011.39
fatcat:q56faeei75a2jmyc4zthaki6f4
Networks-on-chip in emerging interconnect paradigms: Advantages and challenges
2009
2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
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Networks-on-chip (NoCs) have been proposed as a promising solution to simplify and optimize SoC design. ...
Communication plays a crucial role in the design and performance of multi-core systems-on-chip (SoCs). ...
The goal in on-chip communication system design is to transmit data with low latencies and high throughput using the least possible power and resources. ...
doi:10.1109/nocs.2009.5071456
dblp:conf/nocs/CarloniPX09
fatcat:yrli36qr45fopjvu2lf5vuecuy
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