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A Run-Time Dynamic Reconfigurable Computing System for Lithium-Ion Battery Prognosis

Shaojun Wang, Datong Liu, Jianbao Zhou, Bin Zhang, Yu Peng
2016 Energies  
Our research focuses on the lithium-ion battery RUL estimation with a RVM algorithm implemented on a novel FPGA-based dynamic reconfigurable computing architecture.  ...  Most lithium-ion battery RUL estimations are currently implemented on PC platforms.  ...  Execution time depends on computing delay of the task with given computing resources. Number of reconfiguration must be minimized to increase the efficiency.  ... 
doi:10.3390/en9080572 fatcat:mbnenpyknrg3fa4f4vhjyn5obm

Chimera

Emekcan Aras, Stéphane Delbruel, Fan Yang, Wouter Joosen, Danny Hughes
2021 ACM Transactions on Internet of Things  
To tackle this problem, this article presents Chimera, a low-power platform for research and experimentation with reconfigurable hardware for the IoT end-devices.  ...  This diversity in requirements motivates the need for adaptable end-devices, which can be re-configured and re-used throughout their lifetime to handle computation-intensive tasks without sacrificing battery  ...  Secondly, Chimera aims to design a power-efficient device with minimal active and sleep power consumption, which can last for multiple years on standard battery pack.  ... 
doi:10.1145/3440995 fatcat:rmevegcqdrgobigxr2ytggsh3e

Reconfiguration Strategies for Environmentally Powered Devices: Theoretical Analysis and Experimental Validation [chapter]

Alex E. Şuşu, Michele Magno, Andrea Acquaviva, David Atienza, Giovanni De Micheli
2007 Lecture Notes in Computer Science  
Gate Array (FPGA) fabric such that it executes more efficiently the tasks of the application.  ...  Our results show that the systems improve their processing capabilities if suitable reconfiguration strategies are defined for their respective configuration environments.  ...  We execute the SVM task on the AVR microcontroller, since it can perform fast multiplications, and the SVM task is multiplication intensive.  ... 
doi:10.1007/978-3-540-71528-3_21 fatcat:fsa2gfby7fbflm7w6iwqhj7zd4

Review of recent trends in Coarse Grain Reconfigurable Architectures for signal processing applications

Sridharan M.., R. Ramya
2018 Advances in Systems Science and Applications  
Also, the constraints on memory bandwidth in the traditional von Neumann architectures along with the slow growth in the battery capacity demands a paradigm shift in computer architecture design.  ...  Coarse grained reconfigurable architecture got the attention of researchers working in designing computing architectures for processing massive streaming data associated with the multimedia applications  ...  In many cases, the computing task involved in stream processing can be decomposed into multiple stages.  ... 
doi:10.25728/assa.2018.18.1.508 fatcat:eihxjjbe5fbtfidecoa4j7sv6y

Protean

Abu Bakar, Rishabh Goel, Jasper de Winkel, Jason Huang, Saad Ahmed, Bashima Islam, Przemysław Pawełczak, Kasım Sinan Yıldırım, Josiah Hester
2022 Proceedings of the 20th ACM Conference on Embedded Networked Sensor Systems  
An adaptive task-based runtime system, Chameleon, provides intermittency-proof execution of machine learning tasks across heterogeneous processing elements.  ...  can execute data-intensive machine learning tasks, but add complexity across the stack when dealing with intermittent power.  ...  ACKNOWLEDGMENTS We would like to thank Brian Rush and the MAX78000 team at Analog Devices for pointers on working with the accelerator chip and SDK, we thank Tommy Cohen for assistance with all graphics  ... 
doi:10.1145/3560905.3568561 fatcat:pxjzwl6utraijhgr5brmwlikfi

Reconfigurable computing for future vision-capable devices

Miguel Bordallo Lopez, Alejandro Nieto, Olli Silven, Jani Boutellier, David Lopez Vilarino
2015 2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)  
The results show that the inclusion of reconfigurable platforms on mobile devices can enable the computation of several computationally heavy tasks with high performance and small energy consumption while  ...  In this context, the integration of reconfigurable architectures on mobile devices allows dynamic reconfiguration to match the computation and data flow of interactive applications, demonstrating significant  ...  To exploit task parallelism, other architectures are designed with the focus on the execution of different tasks at the same time [7] [8] .  ... 
doi:10.1109/samos.2015.7363657 dblp:conf/samos/LopezNSBV15 fatcat:ljzx4e4iv5a6jidj2abdwcefo4

Dynamic Reconfiguration in Mobile Systems [chapter]

Gerard J.M. Smit, Paul J.M. Havinga, Lodewijk T. Smit, Paul M. Heysters, Michel A.J. Rosien
2002 Lecture Notes in Computer Science  
Dynamically reconfigurable systems have the potential of realising efficient systems as well as providing adaptability to changing system requirements.  ...  Such systems are suitable for future mobile multimedia systems that have limited battery resources, must handle diverse data types, and must operate in dynamic application and communication environments  ...  Multiple processes can coexist in parallel on different tiles. Each processor tile contains five reconfigurable ALUs, 10 local memories, a control unit and a communication unit.  ... 
doi:10.1007/3-540-46117-5_19 fatcat:n73jyodbzvdj3jw7pp24d33zke

Power Modeling and Exploration of Dynamic and Partially Reconfigurable Systems

Robin Bonamy, Sébastien Bilavarn, Daniel Chillet, Olivier Sentieys
2016 Journal of Low Power Electronics  
Results allow to identify low energy / high performance mappings, and by extension, conditions at which partial reconfiguration can achieve energy efficient application processing.  ...  This formalization is based on pragmatic power consumption models of all the tasks of the application that are derived from real measurements.  ...  ACKNOWLEDGEMENTS This work was carried out under the Open-PEOPLE project, a platform project funded within the framework of the Embedded Systems and Large Infrastructures program (ARPEGE) from ANR, the  ... 
doi:10.1166/jolpe.2016.1448 fatcat:kdx7t4ah2zh3poznc47qn254he

Navigating the electronic landscape: Exploring FPGAs and MCUs architectures in electronic design

Deyu Zhao
2024 Applied and Computational Engineering  
FPGAs emerge as the frontrunners in high-computation endeavors, flexing their computational muscles with finesse.  ...  Armed with this knowledge, they can confidently navigate the intricate landscape of electronics, strategically harnessing the power of these two fundamental building blocks to bring innovation and efficiency  ...  These memory units are designed to ensure that MCUs can operate autonomously, executing tasks without relying on external storage.  ... 
doi:10.54254/2755-2721/47/20241207 fatcat:7ei6ehyc3bc7nlkns6btagcyb4

Reconfiguring Crypto Hardware Accelerators on Wireless Sensor Nodes

Steffen Peter, Oliver Stecklina, Jorge Portilla, Eduardo de la Torre, Peter Langendoerfer, Teresa Riesgo
2009 2009 6th IEEE Annual Communications Society Conference on Sensor, Mesh and Ad Hoc Communications and Networks Workshops  
Switching between ECC with a long key i.e. 571bit and those with short key length e.g. to a key length of 163 bit, has a remarkable effect on the execution time.  ...  This partial reconfiguration will be executed on a Spartan 3 FPGA. The visualization will be done in the following way. Standard motes will be connected to the FPG.  ...  In order to ensure long lifetime of battery powered sensor nodes computational intensive tasks should be realized in hardware.  ... 
doi:10.1109/sahcnw.2009.5172959 fatcat:gugmvv5lgfhyleminxa4w2hcka

Hardware and Software Task Scheduling for ARM-FPGA Platforms

Alexander Dorflinger, Mark Albers, Johannes Schlatow, Bjorn Fiethe, Harald Michalik, Phillip Keldenich, S'andor P. Fekete
2018 2018 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)  
Dynamic Partial Reconfiguration places these hardware tasks in the programmable logic at appropriate times. For an efficient scheduling, it needs to be decided when and where to execute a task.  ...  ARM-FPGA coupled platforms allow accelerating the computation of specific algorithms by executing them in the FPGA fabric.  ...  In general multiple functions are mapped to one processing unit, resulting in a task graph that consists of connected components with different activation periods.  ... 
doi:10.1109/ahs.2018.8541481 dblp:conf/ahs/DorflingerASFMK18 fatcat:vvgfyazdg5fanlmqx6dpvolcvy

Run-time resource management based on design space exploration

Chantal Ykman-Couvreur, Philipp A. Hartmann, Gianluca Palermo, Fabien Colas-Bigey, Laurent San
2012 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '12  
of the platform, used to analyze the GRM efficiency.  ...  A Global Resource Manager (GRM) is running in parallel with the central manager of the application on the host processor of the platform.  ...  DEMONSTRATOR On the platform side, the hardware architecture is based on an MPSoC platform with one core acting as host processor, controlling different processing units (HW/SW).  ... 
doi:10.1145/2380445.2380530 dblp:conf/codes/Ykman-CouvreurHPCS12 fatcat:euow4fd55bhjjbh56qawtgh2mi

Mobile Multimedia Systems [chapter]

Paul J. M. Havinga, Gerard J. M. Smit
2002 Electronic Business and Education  
Dynamically reconfigurable systems offer the potential for realising efficient systems as well as providing adaptability to changing system requirements.  ...  Such systems are suitable for future mobile multimedia systems that have limited battery resources, must handle diverse data types, and must operate in dynamic application and communication environments  ...  Each processor tile contains multiple reconfigurable ALUs, local memories, a control unit and a communication unit. Figure 4 shows a FPFA tile with five ALUs.  ... 
doi:10.1007/978-1-4615-1497-8_15 fatcat:3lb7gqb2yjd5hk2gftyjgnsnsy

Adaptable Security in Wireless Sensor Networks by Using Reconfigurable ECC Hardware Coprocessors

J. Portilla, A. Otero, E. de la Torre, T. Riesgo, O. Stecklina, S. Peter, P. Langendörfer
2010 International Journal of Distributed Sensor Networks  
The application of traditional security schemes on sensor nodes is limited due to the restricted computation capability, low-power availability, and the inherent low data rate.  ...  overhead introduced by the hardware reconfiguration.  ...  When the battery is about to wear out, they reconfigure the FPGA with less power consuming tasks, until energy is finished. Nodes Based on Microcontroller Plus FPGA.  ... 
doi:10.1155/2010/740823 fatcat:ht7vxpykfveq3npsyu6amtaz3m

A Reconfigurable Radio Architecture for Cognitive Radio in Emergency Networks

Qiwei Zhang, Andre Kokkeler, Gerard Smit
2006 2006 European Conference on Wireless Technologies  
In this paper, we propose a heterogenous reconfigurable System-on-Chip (SoC) architecture to enable the evolution from the traditional software defined radio to Cognitive Radio.  ...  In the scope of the Adaptive Adhoc Freeband (AAF) project, an emergency network built on top of Cognitive Radio is proposed.  ...  To support multiple services, different constraints on QoS have to be met. 2) the radio needs to be robust to combat bad physical channel conditions. 3) energy-efficiency is a concern because the battery  ... 
doi:10.1109/ecwt.2006.280428 fatcat:lhfzzrdt65gj3ilz7ypbfusawu
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