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Are Coarse-Grained Overlays Ready for General Purpose Application Acceleration on FPGAs?
2016
2016 IEEE 14th Intl Conf on Dependable, Autonomic and Secure Computing, 14th Intl Conf on Pervasive Intelligence and Computing, 2nd Intl Conf on Big Data Intelligence and Computing and Cyber Science and Technology Congress(DASC/PiCom/DataCom/CyberSciTech)
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That is, instead of the requirement for a full cycle through the FPGA vendor tools, overlay architectures present a simpler problem, that of programming an interconnected array of FUs. ...
Despite numerous efforts in reducing reconfiguration times and improving CAD tool support for dynamic reconfiguration of FPGA fabric [16] , [13] , the implementation of rapidly reconfigurable hardware ...
doi:10.1109/dasc-picom-datacom-cyberscitec.2016.110
dblp:conf/dasc/JainMF16
fatcat:gmiz7uunpbaatjryzjiozj24om
Performance Evaluation of Hybrid Reconfigurable Computing Architecture over Symmetrical FPGA
2012
International Journal of Embedded Systems and Applications
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We identified Hybrid LUTs/PLAs architectures as Hybrid Reconfigurable Computing Architectures (HRCA). ...
Reconfigurable computing using FPGA devices provide a method to utilize the available logic resources on the chip for various computations. ...
In full fabricated FPGA chips, 10% of the FPGA is made of logic blocks and other 90% of the FPGA is made of the programmable interconnects network, which form a programmable routing architecture that provides ...
doi:10.5121/ijesa.2012.2312
fatcat:ntyrmdbizza6pl3q546imtgytu
On-the-fly reconfigurable logic
2005
Smart Structures, Devices, and Systems II
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To address the drawbacks of existing RC technologies we propose a generic architecture we call "OFRL" (On-the-Fly Reconfigurable Logic). ...
Our objective is to provide a low power, high speed platform for reconfigurable circuit and dynamically reconfigurable logic applications that use fewer transistors than existing technologies. ...
Dynamic Interconnect Switch Core (DISC) For the OFRL interconnect we propose a special switch called the "DISC" (Dynamic Interconnect Switch Core). ...
doi:10.1117/12.582429
fatcat:z7uru3g6pzdsnoc6yqiwhxn4dy
On-FPGA Communication Architectures and Design Factors
2006
2006 International Conference on Field Programmable Logic and Applications
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The recent development of Platform-FPGA or Field-Programmable System-on-Chip architectures, with immersed coarse-grain processors, embedded memories and IP cores, offers the potential for immense computing ...
In this paper, we survey the state-of-the-art on-FPGA communication architectures and methodologies. ...
Bus Architectures with Run-Time Reconfiguration In [31] , Sedcole et. al. proposed a structured methodology for rapid development of FPGA-based systems. ...
doi:10.1109/fpl.2006.311209
dblp:conf/fpl/MakSCL06
fatcat:xmwjluwdpva4bnm2abhitvtvce
Evolution in architectures and programming methodologies of coarse-grained reconfigurable computing
2009
Microprocessors and microsystems
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systems, the architectures of reconfigurable devices have evolved to coarse-grained compositions of functional units or program controlled processors, which are operated in a coordinated manner to improve ...
In this survey we explore the field of coarse-grained reconfigurable computing on the basis of the hardware aspects of granularity, reconfigurability, and interconnection networks, and discuss the effects ...
Dan Hammerstrom) for their valuable feedback during the internal review of the paper. ...
doi:10.1016/j.micpro.2008.10.003
fatcat:k4c63f4k2zbc5a4mfr3vfwqkfe
Simulation of hybrid computer architectures: simulators, methodologies and recommendations
2007
2007 IFIP International Conference on Very Large Scale Integration
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Index Terms-Simulation, modeling of hybrid computer architectures, simulation of multiprocessor systems, simulation of FPGAs ...
It is essential to investigate the computer architecture of such hybrid computing machines that utilize reconfigurable logic coprocessors as application accelerators in a HPC system. ...
. 2) Reconfigurable logic coprocessors.
3) System interconnects and global interconnects: It is crucial to model system interconnects to a certain degree of fidelity. ...
doi:10.1109/vlsisoc.2007.4402490
dblp:conf/vlsi/VaidyaL07
fatcat:kzamgosiyndxnec6lhos7pbmru
Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10)
2012
International Journal of Reconfigurable Computing
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We hope that you will find in this Special Issue a valuable source of information to your future research. ...
We thank all the authors who contributed to this Special Issue for submitting their manuscript and sharing their latest research results. ...
In "A Dynamically Reconfigured Multi-FPGA Network Platform for High-Speed Malware Collection", S. Mühlbach and A. Kock refine the base NetStage architecture for better management and scalability. ...
doi:10.1155/2012/319827
fatcat:konar3542ndydjcdtgdjk3vmx4
Dynamic partial reconfiguration of 2-D Haar wavelet transform (HWT) for face recognition systems
2011
2011 IEEE 15th International Symposium on Consumer Electronics (ISCE)
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The proposed architectures comprises 2-D HWT with transpose-based computation and dynamic partial reconfiguration (DPR) that have been synthesised using VHDL and implemented on Xilinx Virtex-5 FPGAs. ...
To evaluate the proposed architecture, comparison for both configurations and a detailed performance analysis in terms of area, power consumption and maximum frequency are also addressed in this paper. ...
RESULTS AND ANALYSIS FPGA implementation results for both architectures, analysis and an overview of the advantages offered with DPR technique are presented in the following subsections. ...
doi:10.1109/isce.2011.5973772
fatcat:iozfauegw5bajb4xiipsnj6ouu
Recon.gurable Computing and Digital Signal Processing
[chapter]
2001
Signal Processing and Communications
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This paper presents a survey of academic research and commercial development in reconfigurable computing for DSP systems over the past fifteen years. ...
It is shown that while contemporary reconfigurable computing can be applied to a variety of DSP applications including video, audio, speech, and control, much work remains to realize its full potential ...
Figure 6 , taken from [99] , shows an architecture containing an array of DSP cores, a RISC microprocessor, large amounts of uncommitted SRAM, a reconfigurable FPGA fabric and a reconfigurable interconnection ...
doi:10.1201/9780203908068.ch4
fatcat:d6gyesol3bc4rfwc7r4g5wf2ri
The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units
2008
International Journal of Reconfigurable Computing
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The results show that (1) FPUs should have a square aspect ratio; (2) they should be positioned near the center of the FPGA; (3) their I/O pins should be arranged around all four sides of the FPU; (4) ...
The hybrid FPGAs with embedded memory required 12% wider channels than the case where embedded memory is not used. ...
Acknowledgment The support of UK Engineering and Physical Sciences Research Council (EP/D060567/1 and EP/C549481/1), Agility Celoxica and Xilinx are gratefully acknowledged. ...
doi:10.1155/2008/736203
fatcat:b362rqkxtnexlcqgr476f422wa
Subframe multiplexing for FPGA manufacturing test configuration
2004
Proceeding of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays - FPGA '04
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Multi-context FPGAs are a convenient solution for run-time reconfiguration, but they suffer from large area occupation. ...
This realization can give us speed-up by factor ~2 for hybrid FPGA/CPU realization in comparison with CPU-only implementation. ...
A Left-Edge Algorithm Approach for Scheduling and Allocation of Hardware Contexts in Dynamically Reconfigurable Architectures
Power Analysis and Estimation Tool integrated with XPOWER Dirk Eilers, Helmut ...
doi:10.1145/968280.968315
dblp:conf/fpga/Chmelar04
fatcat:bkkwooxvszbvlfrg4b7h5svtvi
A Circuit and Architecture Codesign Approach for a Hybrid CMOS–STTRAM Nonvolatile FPGA
2011
IEEE transactions on nanotechnology
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Simulation results show improvement of 44.39% in logic area and 22.28% in delay of a configurable logic block (CLB) and average improvement of 16.1% dynamic power over a conventional CMOS FPGA design for ...
In this paper, we propose a novel CMOS-STTRAM hybrid FPGA framework, identify the key design challenges, and propose optimization techniques at circuit, architecture, and application mapping levels. ...
Fig. 3 . 3 Proposed scheme for integration of STTRAM in the CLB and programmable interconnects of a CMOS-STTRAM hybrid FPGA architecture. ...
doi:10.1109/tnano.2010.2041555
fatcat:l5cn4cjskvfw7f7rq45ih47rba
Modeling Reconfigurable Systems-on-Chips with UML MARTE Profile: An Exploratory Analysis
2010
2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools
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Our contributions permit us to model fine grain reconfigurable FPGA based SoC architectures while extending the profile to integrate new features such as Partial Dynamic Reconfiguration supported by these ...
Reconfigurable FPGA based Systems-on-Chip (SoC) architectures are increasingly becoming the preferred solution for implementing modern embedded systems, due to their flexible nature. ...
A. General FPGA architectural details FPGAs usually consist of two layers. ...
doi:10.1109/dsd.2010.58
dblp:conf/dsd/CherifQMD10
fatcat:mpqawo3xnfgbbkvoufrlmoaifa
A 56 Gbaud Reconfigurable Fpga Feed-Forward Equalizer For Optical Datacenter Networks With Flexible Baudrate- And Modulation-Format
2017
Zenodo
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An FPGA-based feed-forward equalizer (FFE) reconfigurable in baudrate and modulation-format is demonstrated. ...
With optically-switched datacenter architectures gaining momentum, reconfigurable equalizers are sought allowing the receiver to adapt to different fiber lengths, bitrates and modulation-formats associated ...
University of Munich for providing the VCSEL. ...
doi:10.5281/zenodo.290566
fatcat:2myz6xthcbbhlfxyi2kaash2e4
The Coarse-Grained / Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units
2008
2008 4th Southern Conference on Programmable Logic
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The results show that (1) FPUs should have a square aspect ratio; (2) they should be positioned near the center of the FPGA; (3) their I/O pins should be arranged around all four sides of the FPU; (4) ...
The hybrid FPGAs with embedded memory required 12% wider channels than the case where embedded memory is not used. ...
Acknowledgment The support of UK Engineering and Physical Sciences Research Council (EP/D060567/1 and EP/C549481/1), Agility Celoxica and Xilinx are gratefully acknowledged. ...
doi:10.1109/spl.2008.4547733
fatcat:dwmvwbb6yve7nnuk3jbzeirf4m
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