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Synthesis of power-optimized and area-optimized circuits from hierarchical behavioral descriptions
1998
Proceedings of the 35th annual conference on Design automation conference - DAC '98
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We present a fast and efficient algorithm for mapping multiple behaviors onto the same RTL module during the course of synthesis, thus allowing our synthesis system to explore previously unexplored regions ...
We present a technique for synthesizing power-as well as area-optimized circuits from hierarchical data flow graphs under throughput constraints. ...
Introduction High-level synthesis is the process of deriving an optimized register-transfer level (RTL) architecture from a behavioral description, usually specified as a data flow graph (DFG) for datadominated ...
doi:10.1145/277044.277167
dblp:conf/dac/LakshminarayanaJ98a
fatcat:ycml4nt5r5eedoexi6hkdl3f3e
Survey On Scheduling And Allocation In High Level Synthesis
2012
International Journal of Computer Science & Engineering Survey
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This paper presents the detailed survey of scheduling and allocation techniques in the High Level Synthesis (HLS) presented in the research literature. ...
It also presents the methodologies and techniques to improve the Speed, (silicon) Area and Power in High Level Synthesis, which are presented in the research literature. ...
ACKNOWLEDGEMENTS We thank to the anonymous reviewers for their numerous insightful and constructive comments.
Authors Dr.M.Joseph received his PhD degree in Computer Engineering from National ...
doi:10.5121/ijcses.2012.3503
fatcat:4uehu4ufxfbmdiozesymmzavpy
A methodology and algorithms for the design of hard real-time multitasking ASICs
1999
ACM Transactions on Design Automation of Electronic Systems
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Our hierarchical approach starts from an incompletely-specified preliminary solution and uses, interchangeably, operating system and behavioral synthesis techniques to derive increasingly more detailed ...
Traditional high-level synthesis concentrates on the implementation of a single task (e.g. filter, linear controller, A/D converter). ...
The Synthesis Problem We focus on exploring synthesis and optimization issues during behavioral synthesis of application-specific systems at the task hardware-sharing level. ...
doi:10.1145/323480.323491
fatcat:pbubnlrrmzgdnerlvg55qqapwq
Resource sharing in hierarchical synthesis
1997
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97
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This allows an efficient specification of less area consuming hierarchical designs while synthesis time can be reduced. ...
This paper presents a new approach to hierarchical high-level synthesis with respect to internal register-transfer structures of complex components. ...
This paper addresses the problem of optimized integration of already synthesized system specifications as complex register-transfer components, in the further high-level synthesis flow. ...
doi:10.1109/iccad.1997.643537
dblp:conf/iccad/BringmannR97
fatcat:wsodr5bgxnc5dhatqu3nux5aii
High-level Synthesis for Low-power Design
2015
IPSJ Transactions on System LSI Design Methodology
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Along this line, high-level synthesis (HLS) is a promising technology to improve design productivity and enable new opportunities for power optimization for higher design quality. ...
We provide an in-depth coverage of HLS low-power optimization techniques and synthesis algorithms proposed in the last decade. ...
Acknowledgments We thank the editorial committee for their helpful comments. ...
doi:10.2197/ipsjtsldm.8.12
fatcat:enmfcevf55bcnak3vxmlmt3eu4
Partitioning and optimizing controllers synthesized from hierarchical high-level descriptions
1998
Proceedings of the 35th annual conference on Design automation conference - DAC '98
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This paper describes methods for partitioning and optimizing controllers described by hierarchical high-level descriptions. ...
High-Level Controller Description ...
The hierarchical high-level specification for this design comprised about 70 compositional constructs. ...
doi:10.1145/277044.277239
dblp:conf/dac/SeawrightM98
fatcat:f2zg4dbxrrbtjio57vqorkjiku
Challenges and opportunities of ESL design automation
2012
2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology
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Such an improvement in efficiency is much needed for design in the deep submicron era. ...
This paper identifies a set of key challenges in ESL design automation with major focus on high-level synthesis (HLS). ...
3 Such high-level ODC information can hardly be derived from RTL in an efficient and complete manner. ...
doi:10.1109/icsict.2012.6467670
fatcat:6cium5rwsjhsteh46ip6bnbxjy
Synthesis-for-testability using transformations
1995
Proceedings of the 1995 conference on Asia Pacific design automation (CD-ROM) - ASP-DAC '95
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We address the problem of transforming a behavioral specification so that synthesis of a testable implementation from the new specification requires significantly less area and partial scan cost than synthesis ...
from the original specification. ...
Transformations have been successfully used in high level synthesis for optimization of variety of goals [36, 5, 33]. ...
doi:10.1145/224818.224961
dblp:conf/aspdac/PotkonjakDR95
fatcat:vtyplftcwjfp3h56e4nsfdozzq
Recent developments in high-level synthesis
1997
ACM Transactions on Design Automation of Electronic Systems
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We then describe some basic techniques for various subtasks of high-level synthesis. ...
We survey recent developments in high level synthesis technology for VLSI design. The need for higher-level design automation tools are discussed first. ...
We define high-level synthesis (HLS) as a translation process from a behavioral description into a register-transfer-level (RTL) structural description. ...
doi:10.1145/250243.250245
fatcat:rtry5zc5y5gjbftnhetwxvvn7a
Architectural Synthesis with Interconnection Cost Control
[chapter]
2000
IFIP Advances in Information and Communication Technology
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Keywords: Architectural synthesis tools map algorithms to architectures under various constraints and quickly providc estimations of area and performance. ...
One of the high-level synthesis characteristics is an "optimal" reusing (sharing) of the operators and the registers. ...
From one behavioral specification, one mapping technology and one real time constraint, an optimised architecture is synthesised [3, 4] , The generic architecture model is composed of tour functional ...
doi:10.1007/978-0-387-35498-9_45
fatcat:4cpglcvadfhdddnboxd3jvnnyy
An Introduction to High-Level Synthesis
2009
IEEE Design & Test of Computers
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Key concepts Starting from the high-level description of an application, an RTL component library, and specific design constraints, an HLS tool executes the following tasks (see Figure 1 ): 1. compiles ...
Catapult C synthesis Catapult takes an algorithm written in ANSI C++ and a set of user directives as input and generates an RTL that is optimized for the specified target technology. ...
doi:10.1109/mdt.2009.69
fatcat:5wa4gs37krgzziwtiftffzszqe
A proposed synthesis method for Application-Specific Instruction Set Processors
2015
Microelectronics Journal
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The new solution is based on a novel abstract ASIP model and a modeling language (Algorithmic Microarchitecture Description Language, AMDL) optimized for this architecture model. ...
Contrary to this, the final register-transfer level models are usually created, at least partly, manually. This paper presents a novel approach for automated hardware model generation for ASIPs. ...
ASICs provide favorable energy-efficiency and high computation performance since they are optimized for a specific function. ...
doi:10.1016/j.mejo.2015.01.001
fatcat:6gu6fd2stnbpvcpfugaku3cnje
FPGA Latency Optimization Using System-level Transformations and DFG Restructuring
2013
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013
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The algorithm is time efficient and can be used for fast design space exploration. ...
This paper describes a system-level approach to improve the latency of FPGA designs by performing optimization of the design specification on a functional level prior to highlevel synthesis. ...
and behavioral level specifications. ...
doi:10.7873/date.2013.316
dblp:conf/date/Gomez-PradoCT13
fatcat:orwlzfj3rvb3zpdnffrudsadla
Introduction to high-level synthesis
1994
IEEE Design & Test of Computers
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Key concepts Starting from the high-level description of an application, an RTL component library, and specific design constraints, an HLS tool executes the following tasks (see Figure 1 ): 1. compiles ...
Catapult C synthesis Catapult takes an algorithm written in ANSI C++ and a set of user directives as input and generates an RTL that is optimized for the specified target technology. ...
doi:10.1109/54.329454
fatcat:xob6dmmhjngvfh7d6f7jpv35ly
Matisse: an architectural design tool for commodity ICs
1998
IEEE Design & Test of Computers
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For example, sometimes the structural design is created from a scheduled algorithmic behavior. Sometimes the schedule is created from an algorithmic behavior and a target structure. ...
an algorithmic specification. ...
doi:10.1109/54.679205
fatcat:te2s27bmtncafafa6zdorzqo4m
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