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Reducing jitter in embedded systems employing a time-triggered software architecture and dynamic voltage scaling
2006
IEEE transactions on computers
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Pont who has guided and encouraged me over the last four years. I have enjoyed working with him and am very grateful for all his wonderful support. ...
Abstract This thesis is concerned with the development o f single-processor embedded systems in which there are requirements for both low CPU energy consumption and low levels of task jitter. ...
-J. and Herkert, A. (1996) ...
doi:10.1109/tc.2006.29
fatcat:uxl6rxhwg5dvfhspyodwii67eq
Design of Reliable and Secure Network-On-Chip Architectures
2015
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A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2016; you can also visit the original URL.
The file type is application/pdf.
aging effects and meet secure design stipulations while maintaining modest power-performance overheads. ...
This dissertation demonstrates design techniques that address both reliability and security issues facing modern NoC architectures. ...
In FoREVER, a bare bones light-weight checker network is used to alert system. ...
doi:10.26076/027f-6b3e
fatcat:hbilmi5whrbqdbly6nxbacebsu