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Accounting for various register allocation schemes during post-synthesis verification of RTL designs
1999
Proceedings of the conference on Design, automation and test in Europe - DATE '99
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This paper reports a formal methodology for verifying a broad class of synthesized register-transfer-level (RTL) designs by accommodating various register allocation/optimization schemes commonly found ...
We propose a formalization of dynamic variable-register mapping, and techniques based on symbolic analysis and higher-order logic theorem proving for verifying synthesized RTL designs. ...
We extend the class of verifiable designs by accommodating various register allocation-optimization schemes. ...
doi:10.1145/307418.307493
fatcat:lfxzf277ivhj3b7lt5mi7oglbu
Accounting for various register allocation schemes during post-synthesis verification of RTL designs
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)
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This paper reports a formal methodology for verifying a broad class of synthesized register-transfer-level (RTL) designs by accommodating various register allocation/optimization schemes commonly found ...
We propose a formalization of dynamic variable-register mapping, and techniques based on symbolic analysis and higher-order logic theorem proving for verifying synthesized RTL designs. ...
We extend the class of verifiable designs by accommodating various register allocation-optimization schemes. ...
doi:10.1109/date.1999.761126
dblp:conf/date/MansouriV99
fatcat:uv2usyuqr5ggbgs6nf72hotnyu
Towards Secure Composition of Integrated Circuits and Electronic Systems: On the Role of EDA
[article]
2020
arXiv
pre-print
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Despite various promising studies, we argue that some aspects still require more efforts, for example: effective means for compilation of assumptions and constraints for security schemes, all the way from ...
the system level down to the "bare metal"; modeling, evaluation, and consideration of security-relevant metrics; or automated and holistic synthesis of various countermeasures, without inducing negative ...
Overall, we call for paradigms like secure by design and secure composition of hardware, i.e., for efforts to account holistically for security notions along with traditional notions of design optimization ...
arXiv:2001.09672v1
fatcat:72lodqrfhfeanfnatkzkjuoc2i
Case Study: First-Time Success ASIC Design Methodology Applied to a Multi-Processor System-on-Chip
[chapter]
2018
Application Specific Integrated Circuits - Technologies, Digital Systems and Design Methodologies [Working Title]
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The use of electronic design automation (EDA) software during each step of the design methodology is also presented. ...
The MPSoC project is initiated by Universiti Tunku Abdul Rahman (UTAR) VLSI design center. The proposed methodology includes the use of Universal Verification Methodology (UVM). ...
Design synthesis The synthesis process is done to the Verilog RTL of RUMPS401 that are completed and fully verified. Design synthesis requires vendor specific synthesis libraries. ...
doi:10.5772/intechopen.79855
fatcat:vff3ewqmmzfnrpxgr2eyo2g5ye
Exploiting Implementation Diversity and Partial Connection of Routers in Application-Specific Network-on-Chip Topology Synthesis
2014
IEEE transactions on computers
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Two different approaches, the post-process approach and the in-process approach, are proposed for exploiting the implementation diversity to provide flexibility between synthesis time and design quality ...
Also, the proposed method for characterizing and modeling routers makes it feasible to consider the implementation diversity even when the partial connection of routers is considered during the synthesis ...
The topographical synthesis is performed for the RTL synthesis to minimize inaccuracy of the frontend-only characterization, using Synopsys Design Compiler and 90nm design kit. ...
doi:10.1109/tc.2012.294
fatcat:y7bnn4i5fzbojifzl7pl2j5i2i
High-Level Synthesis for FPGAs: From Prototyping to Deployment
2011
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Escalating System-on-Chip design complexity is pushing the design community to raise the level of abstraction beyond RTL. ...
for FPGA designs. ...
However, names in HDL are often transformed during RTL synthesis and technology mapping. ...
doi:10.1109/tcad.2011.2110592
fatcat:rr75vomr6zf5vhgs3swjblslza
A reconfigurable neural network ASIC for detector front-end data compression at the HL-LHC
[article]
2021
arXiv
pre-print
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The design is achieved through the use of high-level synthesis tools and the hls4ml framework, and was processed through synthesis and physical layout flows based on a LP CMOS 65 nm technology node. ...
This is the first radiation tolerant on-detector ASIC implementation of a neural network that has been designed for particle physics applications. ...
We acknowledge the Fast Machine Learning collective as an open community of multi-domain experts and collaborators. This community was important for the development of this project. ...
arXiv:2105.01683v1
fatcat:a4beskmvirelbfcdtuvbbarjjm
Optimized RTL Code Generation from Coarse-Grain Dataflow Specification for Fast HW/SW Cosynthesis
2007
Journal of Signal Processing Systems
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In the proposed design methodology, a dataflow graph can be mapped to various hardware structures by changing the resource allocation and schedule information. ...
This paper presents a new methodology of automatic RTL code generation from coarse-grain dataflow specification for fast HW/SW cosynthesis. ...
The ICT and ISRC at Seoul National University and IDEC provided research facilities for this study. Note 1. ...
doi:10.1007/s11265-007-0070-9
fatcat:4qsh2rjcorg6blsjneko274nsy
Rethinking Watermark: Providing Proof of IP Ownership in Modern SoCs
[article]
2022
IACR Cryptology ePrint Archive
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Unfortunately, prior work has been built upon assumptions that cannot be met within the modern SoC design and verification processes. ...
The threat posed by IP piracy and overuse has been a topic of research for the past decade or so and has led to creation of a field called watermarking. ...
[26] proposed watermark insertion during register allocation. ...
dblp:journals/iacr/AnandakumarRRKD22
fatcat:62djo73tt5bivcvinr6kky3dsq
MATLAB as a Design and Verification Tool for the Hardware Prototyping of Wireless Communication Systems
[chapter]
2012
MATLAB - A Fundamental Tool for Scientific Computing and Engineering Applications - Volume 2
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It is important to note that this chapter will not cover model-based, MATLAB-to-Register Transfer Level (RTL) design flows (e.g., by using the Simulink and System Generator tools). ...
Adversely, a custom-code programming strategy will be followed, where the user carefully designs each component of the system and takes into account the constraints of real-world hardware and signals. ...
Even if equivalent HDL constructs exist, they are used during simulation time but do not serve for logic synthesis (e.g., a for-loop construct with undefined number of iterations). ...
doi:10.5772/48706
fatcat:ipmfztmvjnagnmt2aigbu75vsq
Application driven network-on-chip architecture exploration & refinement for a complex SoC
2011
Design automation for embedded systems
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This article presents an overview of the design process of an interconnection network, using the technology proposed by Arteris. ...
Section 3 describes the proposed top-down approach, based on the progressive refinement of the NoC description, from its functional specification (Sect. 4) to its verification (Sect. 8). ...
At the end of this phase, the Register Transfer Level (RTL) description of the NoC can be exported together with synthesis scripts, ready to be integrated, simulated and synthesized. • In the verification ...
doi:10.1007/s10617-011-9075-5
fatcat:m6tuyuj37babdgdorie6hchzge
Using ACL2 to Verify Loop Pipelining in Behavioral Synthesis
2014
Electronic Proceedings in Theoretical Computer Science
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Behavioral synthesis involves compiling an Electronic System-Level (ESL) design into its Register-Transfer Level (RTL) implementation. ...
Loop pipelining is one of the most critical and complex transformations employed in behavioral synthesis. ...
Introduction Behavioral synthesis is the process of synthesizing an Electronic System-level (ESL) specification of a hardware design into an RTL implementation. ...
doi:10.4204/eptcs.152.10
fatcat:he3mzivs75eyjbfof6rovco7k4
Verilog HDL and its ancestors and descendants
2020
Proceedings of the ACM on Programming Languages (PACMPL)
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For large-scale digital logic design, previous schematic-based techniques have transformed into textual registertransfer level (RTL) descriptions written in Verilog. ...
Since its creation in 1984 and first sale in 1985, Verilog has completely revolutionized the design of hardware. Verilog enabled the development and wide acceptance of logic synthesis. ...
Developed by Synopsys in 1987 and grew to dominate the RTL synthesis market. DFT Design for test, or design for testability. ...
doi:10.1145/3386337
fatcat:ttezkcr6pzgppbeofpi23vu2wy
A dynamically reconfigurable asynchronous processor for low power applications
2010
2010 Conference on Design and Architectures for Signal and Image Processing (DASIP)
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The architecture maintains most of the benefits of custom asynchronous design, while also providing programmability via conventional high-level languages. ...
When compared to an equivalent synchronous design, our processor results in a power reduction of up to 18%. ...
This research is sponsored by the Overseas Research Student Awards Scheme (ORSAS) and by Edinburgh University's Institute for Integrated Micro and Nano Systems (IMNS). ...
doi:10.1109/dasip.2010.5706249
dblp:conf/dasip/FawazAKMNLE10
fatcat:2gljh2m66vbetaz6axod2lwjzq
Hardware certification for real-time safety-critical systems: State of the art
2010
Annual Reviews in Control
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A B S T R A C T This paper discusses issues related to the RTCA document DO-254 Design Assurance Guidance for Airborne Electronic Hardware and its consequences for hardware certification. ...
to hardware verification. ...
Findings contained herein are not necessarily those of the FAA. The authors are grateful to the anonymous reviewers for constructive comments. ...
doi:10.1016/j.arcontrol.2009.12.003
fatcat:tqz3ftovubcclcsuu5bypjlelm
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