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RAIDR: Retention-aware intelligent DRAM refresh
2012
2012 39th Annual International Symposium on Computer Architecture (ISCA)
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In this paper, we propose RAIDR (Retention-Aware Intelligent DRAM Refresh), a low-cost mechanism that can identify and skip unnecessary refreshes using knowledge of cell retention times. ...
The negative effects of DRAM refresh increase as DRAM device capacity increases. Existing DRAM devices refresh all cells at a rate determined by the leakiest cell in the device. ...
This research was partially supported by grants from NSF (CA-REER Award CCF-0953246), GSRC, and Intel ARO Memory Hierarchy Program. ...
doi:10.1109/isca.2012.6237001
dblp:conf/isca/LiuJVM12
fatcat:gizsbubpona57kuuksgkjme3ny
RAIDR
2012
SIGARCH Computer Architecture News
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In this paper, we propose RAIDR (Retention-Aware Intelligent DRAM Refresh), a low-cost mechanism that can identify and skip unnecessary refreshes using knowledge of cell retention times. ...
The negative effects of DRAM refresh increase as DRAM device capacity increases. Existing DRAM devices refresh all cells at a rate determined by the leakiest cell in the device. ...
This research was partially supported by grants from NSF (CA-REER Award CCF-0953246), GSRC, and Intel ARO Memory Hierarchy Program. ...
doi:10.1145/2366231.2337161
fatcat:254j7q3mufaldpbtqv4znkihhi
The virtual write queue
2010
SIGARCH Computer Architecture News
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In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. ...
We show that through awareness of the physical main memory layout and by focusing on writes, both read and write average latency can be shortened, memory power reduced, and overall system performance improved ...
The authors acknowledge the use of the Archer infrastructure for their simulations, and Kyu-Hyoun Kim for assistance in DRAM bus utilization calculations. ...
doi:10.1145/1816038.1815972
fatcat:nsztbkb3ifguvkolw25vhet5dq
The virtual write queue
2010
Proceedings of the 37th annual international symposium on Computer architecture - ISCA '10
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In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. ...
We show that through awareness of the physical main memory layout and by focusing on writes, both read and write average latency can be shortened, memory power reduced, and overall system performance improved ...
The authors acknowledge the use of the Archer infrastructure for their simulations, and Kyu-Hyoun Kim for assistance in DRAM bus utilization calculations. ...
doi:10.1145/1815961.1815972
dblp:conf/isca/StuecheliKDHJ10
fatcat:hzdxcjpt6ffp7ism3xgwqsma4a
An experimental study of data retention behavior in modern DRAM devices
2013
Proceedings of the 40th Annual International Symposium on Computer Architecture - ISCA '13
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We discuss possible physical explanations for these phenomena, how their magnitude may be affected by DRAM technology scaling, and their ramifications for DRAM retention time profiling mechanisms. ...
In this paper, we present a comprehensive quantitative study of retention behavior in modern DRAMs. ...
This research was partially supported by grants from NSF (CAREER Award CCF-0953246) and Intel URO Memory Hierarchy Program. ...
doi:10.1145/2485922.2485928
dblp:conf/isca/LiuJKWM13
fatcat:taldqgxgfbh6fnhucisuc2qkj4
An experimental study of data retention behavior in modern DRAM devices
2013
SIGARCH Computer Architecture News
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We discuss possible physical explanations for these phenomena, how their magnitude may be affected by DRAM technology scaling, and their ramifications for DRAM retention time profiling mechanisms. ...
In this paper, we present a comprehensive quantitative study of retention behavior in modern DRAMs. ...
This research was partially supported by grants from NSF (CAREER Award CCF-0953246) and Intel URO Memory Hierarchy Program. ...
doi:10.1145/2508148.2485928
fatcat:7m74mjjporc2ti3j2tcm5xw7aq
Minimalist open-page
2011
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture - MICRO-44 '11
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Contemporary DRAM systems have maintained impressive scaling by managing a careful balance between performance, power, and storage density. ...
DRAM's use is further complicated in many-core systems where the memory interface is shared among multiple cores/threads competing for memory bandwidth. ...
This work is sponsored in part by the National Science Foundation under award 0702694 and CRI collaborative awards: 0751112, 0750847, 0750851, 0750852, 0750860, 0750868, 0750884, 0751091, and by IBM. ...
doi:10.1145/2155620.2155624
dblp:conf/micro/KaseridisSJ11
fatcat:isqtxw73zzga5gprid2gasrnfe
Evaluating STT-RAM as an energy-efficient main memory alternative
2013
2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)
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In this paper, we explore the possibility of using STT-RAM technology to completely replace DRAM in main memory. ...
Our experiments indicate that an optimized, equal capacity STT-RAM main memory can provide performance comparable to DRAM main memory, with an average 60% reduction in main memory energy. ...
This work was partially supported by grants from the National Science Foundation (CAREER Award CCF-0953246, 1147397, 1147388, 1152479, 1017882, 0963839, 0811670, 1205618, 1213052), Intel Corporation URO ...
doi:10.1109/ispass.2013.6557176
dblp:conf/ispass/KultursayKSM13
fatcat:2xtwhg3cfvhppe5myoupvze6pa
The CacheLib Caching Engine: Design and Experiences at Scale
2020
USENIX Symposium on Operating Systems Design and Implementation
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However, this approach ignores the difficult challenges that different caching systems have in common, greatly increasing the overall effort required to deploy, maintain, and scale each cache. ...
CacheLib was first deployed at Facebook in 2017 and today powers over 70 services including CDN, storage, and application-data caches. ...
Acknowledgements This work is supported by NSF-CMMI-1938909, NSF-CSR-1763701, NSF-XPS-1629444, a 2020 Google Faculty Research Award, and a Facebook Graduate Fellowship. ...
dblp:conf/osdi/BergBMGGLUCBHG20
fatcat:hrkka4wk55chfha77yaesspidq
Software Wear Management for Persistent Memories
2019
USENIX Conference on File and Storage Technologies
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to DRAM. ...
Instead, it relies on a novel wear-estimation technique that builds upon Intel's Precise Event Based Sampling to approximately track processor cache contents via a software-maintained Bloom filter and ...
This work was supported by ARM and the National Science Foundation under the award NSF-CCF-1525372. ...
dblp:conf/fast/GogteWDKCNW19
fatcat:krtcsb2lvjb65lopui4jfiutge
A Modern Primer on Processing in Memory
[article]
2022
arXiv
pre-print
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At the same time, conventional memory technology is facing many technology scaling challenges in terms of reliability, energy, and performance. ...
are increasingly data-intensive, and memory bandwidth and energy do not scale well, (2) energy consumption is a key limiter in almost all computing platforms, especially server and mobile systems, (3) ...
approximately 128× while DRAM band-width has improved only approximately 20× [41, 42, 50] , as shown in Figure 1 . ...
arXiv:2012.03112v3
fatcat:zp7uu4uwrbaujjz6ia7bmfn4yy
Micro-pages
2010
SIGARCH Computer Architecture News
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Such co-location can be achieved in many ways, notably involving a reduction in OS page size and software or hardware assisted migration of data within DRAM. ...
Power consumption and DRAM latencies are serious concerns in modern chip-multiprocessor (CMP or multi-core) based compute systems. ...
This work was supported in parts by NSF grants CCF-0430063, CCF-0811249, CCF-0702799, CCF-0916436, NSF CAREER award CCF-0545959, Intel, SRC grant 1847.001 and the University of Utah. ...
doi:10.1145/1735970.1736045
fatcat:r5i7xv4wz5a5zfwe6mapxpog34
Micro-pages
2010
Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems - ASPLOS '10
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Such co-location can be achieved in many ways, notably involving a reduction in OS page size and software or hardware assisted migration of data within DRAM. ...
Power consumption and DRAM latencies are serious concerns in modern chip-multiprocessor (CMP or multi-core) based compute systems. ...
This work was supported in parts by NSF grants CCF-0430063, CCF-0811249, CCF-0702799, CCF-0916436, NSF CAREER award CCF-0545959, Intel, SRC grant 1847.001 and the University of Utah. ...
doi:10.1145/1736020.1736045
dblp:conf/asplos/SudanCNABD10
fatcat:gahfs7ticbdhbbnvq4ft2zofza
Micro-pages
2010
SIGPLAN notices
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Such co-location can be achieved in many ways, notably involving a reduction in OS page size and software or hardware assisted migration of data within DRAM. ...
Power consumption and DRAM latencies are serious concerns in modern chip-multiprocessor (CMP or multi-core) based compute systems. ...
This work was supported in parts by NSF grants CCF-0430063, CCF-0811249, CCF-0702799, CCF-0916436, NSF CAREER award CCF-0545959, Intel, SRC grant 1847.001 and the University of Utah. ...
doi:10.1145/1735971.1736045
fatcat:zbbyt5qgx5ce7ami2k7vlnm4ny
Error Characterization, Mitigation, and Recovery in Flash Memory Based Solid-State Drives
[article]
2017
arXiv
pre-print
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This positive growth is a result of two key trends: (1) effective process technology scaling, and (2) multi-level (e.g., MLC, TLC) cell data coding. ...
in flash memory cells. ...
A version of the paper is published as an invited article in Proceedings of the IEEE [11] . This version is almost identical to [11] . ...
arXiv:1706.08642v3
fatcat:ozzc62npvzewhgkb54ebvnh5ta
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