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A dynamically reconfigurable communication architecture for multicore embedded systems
2012
Journal of systems architecture
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Authors requiring further information regarding Elsevier's archiving and manuscript policies are encouraged to visit: t r a c t To deal with the communication bottleneck of multiprocessor systems, several ...
This article appeared in a journal published by Elsevier. ...
Acknowledgments We would like to thank Ömer Çogal for supplying numeric test values for NoC, Smail Niar and Betül Demiröz for their supports, suggestions and corrections in our case studies. ...
doi:10.1016/j.sysarc.2012.02.003
fatcat:w3zrj5nhwrajnihwcuivl4cm2m
A reconfigurable simulator for large-scale heterogeneous multicore architectures
2011
(IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE
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We build a reconfigurable multicore simulator based on M5, an event-driven simulator originally targeting a network of processors. ...
Because of the abundance of potential architectures, an easily reconfigurable multicore simulator is needed to explore the large design space. ...
IIS-0612049 and CNS-0615277, a grant from Intel Research, and a professor partnership award from NVIDIA Research. We would like to thank Jeremy W. ...
doi:10.1109/ispass.2011.5762722
dblp:conf/ispass/MengS11
fatcat:jc7geggvgjdzjozzbxjmndtg2q
Memory-based computing for performance and energy improvement in multicore architectures
2012
Proceedings of the great lakes symposium on VLSI - GLSVLSI '12
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In this paper, we propose a novel reconfigurable MBC framework for multicore architectures where each core uses caches for computation using Look Up Tables (LUTs). ...
architectures. ...
Partitioning
MBC IN MULTICORE SYSTEMS This section presents our RMBC framework for multicore architectures. ...
doi:10.1145/2206781.2206851
dblp:conf/glvlsi/RahmaniMB12
fatcat:4vs5sirdwvhllhpwxvthh5uzhi
Special Issue: Algorithm/Architecture Co-Exploration of Visual Computing on Emerging Platforms
2009
IEEE transactions on circuits and systems for video technology (Print)
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We also thank the authors for their valuable contributions, and the anonymous reviewers for their help in ensuring the quality of the special issue. ...
We would like to thank everyone who submitted papers to the special issue for their efforts, and express our regret that due to limited space and the need for balanced coverage, not all high-quality submissions ...
The second factor considered was on novelties for either multicore and/or reconfigurable architecture. ...
doi:10.1109/tcsvt.2009.2034438
fatcat:4lxefab4njgftpw6ngcpms3odm
A Compilation- and Simulation-Oriented Architecture Description Language for Multicore Systems
2012
2012 IEEE 15th International Conference on Computational Science and Engineering
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Today's reconfigurable multicore architectures become more and more complex. ...
Thus, the toolchain is kept retargetable by using a novel architecture description language (ADL) for multiprocessor system on chip devices. ...
Thus, the toolchain is kept retargetable by using a novel architecture description language (ADL) for multiprocessor system on chip devices. ...
doi:10.1109/iccse.2012.60
dblp:conf/cse/StripfOBKGAVPSDSB12
fatcat:csi5rb4sbfaz7oukt7olsui2fu
ReKonf: Dynamically reconfigurable multiCore architecture
2014
Journal of Parallel and Distributed Computing
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The embedded systems group at CS&E department, in which we have renowned faculty members ...
He has been more of a friend than a mentor who eases out pressure and creates an environment that encourages perseverance, exploration, and excellence. ...
Reconfigurability . . . . . . . . . . . . . 50 3.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4 Design of ReKonf : A Reconfigurable Multicore Architecture 53 4.1 Parameters ...
doi:10.1016/j.jpdc.2014.05.007
fatcat:oufjm5ohv5fgfmdatv5qgw3k4m
Model-Based Deployment of Mission-Critical Spacecraft Applications on Multicore Processors
[chapter]
2013
Lecture Notes in Computer Science
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architectures
-Multicore processors:
+ Exploit parallelism for performance
+ Advanced power management
+ Flexible reconfiguration
-• Trend: Multicore processors
to increase performance in embedded ...
: a manifesto for high integrity software ...
doi:10.1007/978-3-642-38601-5_3
fatcat:vvxevthivbfh3erjbswz2n4k6q
Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores
2014
ACM Transactions on Reconfigurable Technology and Systems
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In our work we build on a recent reference architectural framework as a model for self-aware computing and instantiate it for an FPGA-based heterogeneous multicore running the ReconOS reconfigurable architecture ...
To this end, we use a previously published reference architectural framework [Becker et al. 2011 ] as a model for managing heterogeneous multicores. ...
Fig. 1 . 1 Reference architectural framework for a self-aware compute node [Becker et al. 2012 ].
Fig. 2 . 2 A heterogeneous multicore architecture. ...
doi:10.1145/2617596
fatcat:ep5qzii7xzfofp5yc74m7vkk7u
Algorithm/Architecture Co-Exploration of Visual Computing on Emergent Platforms: Overview and Future Prospects
2009
IEEE transactions on circuits and systems for video technology (Print)
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Concurrently exploring both algorithmic and architectural optimizations is a new design paradigm. ...
This paper shows that seamless weaving of the development of previously autonomous visual computing algorithms and multicore or reconfigurable architectures will unavoidably become the leading trend in ...
Dataflow Modeling and Complexity Characterization for Multicore and Reconfigurable Systems Design In multicore architectures, complexity measurements, especially of the potential for parallelism embedded ...
doi:10.1109/tcsvt.2009.2031376
fatcat:fjcoaodrwffgtgp375rco34oym
Analytical models of Energy and Throughput for Caches in MPSoCs
[article]
2019
arXiv
pre-print
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error of up to 11.5% for both single and multicore architectures. ...
This paper presents an enhanced version of previously proposed cache energy and throughput models for multicore systems. ...
multicore reconfigurable architecture [24] . ...
arXiv:1910.08666v1
fatcat:rxosdhfzkbhhhf3urirgaz4azi
Simulation of hybrid computer architectures: simulators, methodologies and recommendations
2007
2007 IFIP International Conference on Very Large Scale Integration
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In the future, high performance computing systems may consist of multiple multicore processors and reconfigurable logic coprocessors. ...
It is essential to investigate the computer architecture of such hybrid computing machines that utilize reconfigurable logic coprocessors as application accelerators in a HPC system. ...
A. Simulators for Chip Multiprocessors As can be seen in Figure 1 , a node in most of the future hybrid computing systems will contain multiple multicore processors. ...
doi:10.1109/vlsisoc.2007.4402490
dblp:conf/vlsi/VaidyaL07
fatcat:kzamgosiyndxnec6lhos7pbmru
A fuzzy logic based dynamic reconfiguration scheme for optimal energy and throughput in symmetric chip multiprocessors
2010
2010 NASA/ESA Conference on Adaptive Hardware and Systems
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A coarse grained architecture was selected as to be a focus for this study as it typically allows for fast reconfiguration as compared to the finegrained architectures, thus making it more feasible to ...
Embedded systems architectures have traditionally often been investigated and designed in order to achieve a greater throughput combined with minimum energy consumption. ...
Other examples of task scheduling approaches for reconfigurable or multicore architectures could be found in [11] [12] [13] [14] [15] . ...
doi:10.1109/ahs.2010.5546239
dblp:conf/ahs/QadriM10
fatcat:jba6t5io2bcqjig2lgdpg5xcda
Program Execution on Reconfigurable Multicore Architectures
2016
Electronic Proceedings in Theoretical Computer Science
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2016 pre-print arXiv:1606.05944v1 fatcat:b577tlsyunhgxpii7wept3fhci
Based on our earlier abstract operational framework for multicore execution with hierarchical memory structures, we describe execution of multithreaded programs on reconfigurable architectures that support ...
Pal et al. proposed a novel reconfigurable hardware approach for executing multithreaded programs. ...
I wish to acknowledge the helpful discussions with my colleague Kolin Paul who taught me the little I know about reconfigurable architectures. ...
doi:10.4204/eptcs.211.9
fatcat:jxg7nrmj2zg65ajzxa7xqtyocu
Introduction to the Future of Reconfigurable Computing and Processor Architectures
[chapter]
2009
Lecture Notes in Computer Science
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Finally, the session ends with a survey on the use of reconfiguration in multithread architectures. ...
In this special session, selected papers add to the discussion on how this symbiosis will evolve, showing how general-purpose or multicore computing can benefit from reconfiguration, how can one generalize ...
Finally, the session ends with a survey on the use of reconfiguration in multithread architectures. K. Bertels et al. (Eds.): SAMOS 2009, LNCS 5657, p. 226, 2009. ...
doi:10.1007/978-3-642-03138-0_24
fatcat:kw6xug7fm5b3bbcw56laebvrlq
A Self Distributing Virtual Machine for Adaptive Multicore Environments
2009
International journal of parallel programming
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Results for a basic application for both systems are presented. ...
The SDVM has evolved to a virtualization layer for multicore-FPGAs, now called SDVM R . ...
Our discussion in this article focuses on dynamically reconfigurable FPGAs as an implementation architecture for multicore systems. ...
doi:10.1007/s10766-009-0119-4
fatcat:o5s4a2s55jcs3h5ae23x4c5lfy
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