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A high-level synthesis approach to optimum design of self-checking circuits
Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition
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Rather than substituting self-checking units in system synthesized independently of self-checking requirements, we introduce self-checking in high-level synthesis as a requirement already for scheduling ...
We present an innovative solution to design of selfchecking systems implementing arithmetic algorithms. ...
It appears worthwhile to introduce self-checking requirements already in the initial steps of high-level synthesis, modifying the synthesis approach so as to optimize area and performances even while granting ...
doi:10.1109/eurdac.1996.558233
dblp:conf/eurodac/SamiAP96
fatcat:izkitkzab5hbfdmuqz7uwrr4t4
Semiconcurrent error detection in data paths
2001
IEEE transactions on computers
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An innovative approach for high-level synthesis of digital circuits with semi-concurrent selfchecking abilities is introduced, achieving a compromise between redundancy and checking effectiveness. ...
A reference architecture is defined; a technique allowing to reduce redundancy through resource sharing is then introduced, leading to synthesis of the self-checking architecture. ...
In [2, 3] , it was suggested to introduce the self-checking requirements directly from the initial steps of high-level synthesis, modifying the synthesis approach so as to optimise area and performances ...
doi:10.1109/12.926159
fatcat:yc5mqyyk5bagjnibiyxthtij7u
High-efficiency harmonic loaded oscillator with low bias using a nonlinear design approach
1999
IEEE transactions on microwave theory and techniques
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Using the proposed approach, we design an oscillator that has a high efficiency of 61% at 1.86 GHz with a very low bias voltage of 2.0 V. ...
We present a design method for an optimized highefficiency harmonic loaded oscillator. ...
ACKNOWLEDGMENT The authors thank the reviewer for the valuable comments about the concepts of the load line and classes of amplifier. ...
doi:10.1109/22.788608
fatcat:2hotqyablnckrno2e6d46pqodi
On-chip I/sub DDQ/ testing in the AE11 fail-stop controller
1998
IEEE Design & Test of Computers
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In addition, we worked in close cooperation with the universities of Hannover, Erlangen-Nuremberg, and Grenoble. ...
At the end of the self-test, when IDDQ_MS returns to high level, TP3 becomes conductive first. ...
Therefore, we must in-sert the necessary circuitry for online I DDQ testing in an additional design step. We call this approach a two-pass test circuit synthesis flow. ...
doi:10.1109/54.735928
fatcat:uwamhgtr2rbabeht3qfxxnhrki
Approximate logic circuits for low overhead, non-intrusive concurrent error detection
2008
2008 Design, Automation and Test in Europe
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This paper describes a scalable, technology-independent algorithm for the synthesis of approximate logic circuits. ...
CED based on approximate logic circuits does not impose any performance penalty on the original design. ...
Totally self-checking checker Checker design is an integral part of concurrent error detection. ...
doi:10.1109/date.2008.4484789
dblp:conf/date/ChoudhuryM08
fatcat:wwtrjhw5zzcq3ojuufwhsmw2za
Approximate logic circuits for low overhead, non-intrusive concurrent error detection
2008
Proceedings of the conference on Design, automation and test in Europe - DATE '08
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This paper describes a scalable, technology-independent algorithm for the synthesis of approximate logic circuits. ...
CED based on approximate logic circuits does not impose any performance penalty on the original design. ...
Totally self-checking checker Checker design is an integral part of concurrent error detection. ...
doi:10.1145/1403375.1403593
fatcat:74pdw65jinbvvebanyxormuilq
GBOPCAD: a synthesis tool for high-performance gain-boosted opamp design
2005
IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications
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Index Terms-Doublet, equation based, gain boost, gain-boosted opamp computer-aided design (GBOPCAD), global optimum, stability, high-speed opamp, opamp synthesis, sample/hold (S/H) front-end, simulated ...
A systematic design methodology for high-performance gain-boosted opamps (GBOs) is presented. ...
ACKNOWLEDGMENT The authors would like to thank Prof. K. Nagaraj, Texas Instruments, for technical advice and for his reviewing of the manuscript; and Dr. Q. ...
doi:10.1109/tcsi.2005.851718
fatcat:sgnyccmsandwzmqh2zezgyprve
Implementation of Area & Power Optimized VLSI Circuits Using Logic Techniques
2017
IOSR Journal of VLSI and Signal processing
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In second approach, Multi value logic based digital circuit is designed by increasing the representation domain from the two level (N=2) switching algebra to N > 2 levels. ...
The simulation process is carried out by tanner toolv14.11 to check the functionality of the PASTA & MVL circuits. ...
And thereby, the performance in measure of speed of the proposed MVL circuits tend to produce a high output. [14]
VI. ...
doi:10.9790/4200-0704011523
fatcat:tgmlworlwvh3zfgr4xvecbdn2e
Lowering power consumption in concurrent checkers via input ordering
2004
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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As a result, the computational cost of determining the optimum input order can be very expensive as the number of inputs to the checker increases. ...
The inputs of the checker are usually driven by the outputs of the function logic and check symbol generator logic-spatial correlations between these outputs are analyzed to compute an input order that ...
Power, for long a concern confined to the realm of portable systems' design, is today a first-order factor influencing integrated circuit design at all levels of the design flow [14] . ...
doi:10.1109/tvlsi.2004.836318
fatcat:qb4npvwvprhmtfdbewhcnhihha
Built in Self-Test for 4 × 4 Signed and Unsigned Multipliers in FPGA
2014
International Journal of Computer Applications
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reason to incorporate BIST in a circuit. ...
design error that may generate later after synthesis therefore it is always better to do synthesis after simulation process. ...
doi:10.5120/16681-6792
fatcat:sycvmf46pjd4rj332sch5jmpm4
D&T Conferences
1985
IEEE Design & Test of Computers
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Matsuoka of NTT presented a totally self-checking, generalized prediction checker. ...
This strategy was felt to provide a quick sanity check, accelerate the "time-to-market" factor, and make it easier for the customers to inspect purchased circuits. Random-logic self-test. ...
doi:10.1109/mdt.1985.294827
fatcat:pkojrmf5rfatzk4ewa3qhflq5y
Method of the adaptive decoding of self-orthogonal codes in telecommunication
2020
Indonesian Journal of Electrical Engineering and Computer Science
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of formalization of description of method of increasing of noise immunity of telecommunication systems transmitting information to the synthesis and improving receiver circuit modulated signals on the ...
The result of research conducted in the course of the paper is to develop a set of scientifically grounded theoretical positions and practical recommendations and proposals for the development of mechanisms ...
To solve the problem the synthesis of adaptive decoder of self-orthogonal codes was performed. ...
doi:10.11591/ijeecs.v19.i3.pp1287-1296
fatcat:l6qrp35hnra2nb2gehv565zk3i
EDA in IBM: past, present, and future
2000
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Throughout its history, from the early four-circuit gate-array chips of the late 1960s to today's billion-transistor multichip module, IBM has invested in tools to support its leading-edge technology and ...
to enable highly productive system-on-a-chip designs that include widely diverse hardware and software components. ...
In addition, the authors salute the many developers and designers, referenced and not referenced, who have contributed to IBM's EDA systems over the years. ...
doi:10.1109/43.898827
fatcat:4qb63c3ytzbezkzrumy57wbbv4
Optimized is Not Always Optimal - The Dilemma of Analog Design Automation
2022
Proceedings of the 2022 International Symposium on Physical Design
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I will show that the dilemma that arises in analog design with these optimizers is the root cause of the low level of automation in analog design. ...
While the design of the digital parts of the ICs is highly automated, the design of the analog circuitry is largely done manually; it is very time-consuming; and prone to error. ...
If M is low (that is, the level of abstraction is high), there is a good probability of finding a global optimum in the solution space or to find a solution that is nearly optimum (i.e., high Qmod), as ...
doi:10.1145/3505170.3511042
fatcat:x5gt66udpbbnzotjbxgvu5mhdi
Power dissipation, variations and nanoscale CMOS design: Test challenges and self-calibration/self-repair solutions
2007
2007 IEEE International Test Conference
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In this paper, we provide an overview of major low-power and variation-tolerant design techniques; discuss related test issues and focus on effectiveness of self-calibration/self-repair solutions to maintain ...
These problems continue to grow with leakage power becoming a dominant form of power consumption. ...
In [27] , a circuit synthesis approach is proposed that can result low active power dissipation, while enhancing test cost and test confidence. ...
doi:10.1109/test.2007.4437659
dblp:conf/itc/BhuniaR07
fatcat:bdsfonjkkrhnxeigu3gog4y6de
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