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A $\Delta{-}\Sigma$ PLL-Based Spread-Spectrum Clock Generator With a Ditherless Fractional Topology
2009
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
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Without spread-spectrum clocking, the PLL generates 2.4-GHz output with 18.82-ps peak-to-peak jitter. ...
The PLL employs a multiphase divider to implement the modulated fractional counter with increased 1 6 operation speed. ...
In order for the ring to oscillate with an even number of stages, the differential outputs of one of the stages are twisted to introduce an additional inversion. ...
doi:10.1109/tcsi.2008.926975
fatcat:yqroil7hzzdazgbw2kzjle2ipu
An Area-Efficient Multi-Phase Fractional-Ratio Clock Frequency Multiplier
2016
JSTS Journal of Semiconductor Technology and Science
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The proposed FFMDLL provides 8-phase output clocks and achieves a frequency range of 0.6-1.0 GHz with programmable multiplication ratios of N/M, where N = 4, 5, 8, 10 and M = 1, 2, 3. ...
It achieves an effective peak-to-peak jitter of 5 ps and dissipates 3.4 mW from a 1.0 V supply at 1 GHz. ...
To achieve low-jitter fractionalratio clock multiplication with 8-phase output clocks, the proposed architecture adopts a 3-to-1 MUX based switch-control scheme and utilizes a 4-stage differential voltage-controlled ...
doi:10.5573/jsts.2016.16.1.143
fatcat:4l4tbqdtyzhqzjrqovgkikw6nq
A 40-Gb/s clock and data recovery circuit in 0.18-μm CMOS technology
2003
IEEE Journal of Solid-State Circuits
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The oscillator is based on differential excitation of a closed-loop transmission line at evenly spaced points, providing half-quadrature phases. ...
A phase-locked clock and data recovery circuit incorporates a multiphase LC oscillator and a quarter-rate bang-bang phase detector. ...
The multiphase oscillator introduced here is based on the concept of differential stimulus of a closed-loop transmission line at evenly-spaced points, as illustrated conceptually in Fig. 4 (a) with two ...
doi:10.1109/jssc.2003.818566
fatcat:44uqz6sqqbgxnkq55b5gk6gt3u
A Tree-Topology Multiplexer for Multiphase Clock System
2009
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
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In order to verify the feasibility, this proposed design is integrated with a multiphase phase-locked loop and a low-voltage differential signaling driver in a 0.18-m CMOS technology. ...
This paper proposes a tree-topology multiplexer (MUX) that employs a multiphase low-frequency clock rather than a high-frequency clock. ...
In this paper, we propose a multiphase-clock-based tree-topology MUX in order to achieve high speed and low power at the same time. ...
doi:10.1109/tcsi.2008.926578
fatcat:w67nij5xw5fcthhojrhnyl2b4y
A PVT-compensated 2.2 to 3.0 GHz Digitally Controlled Oscillator for All-Digital PLL
2014
JSTS Journal of Semiconductor Technology and Science
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We describe a digitally controlled oscillator (DCO) which compensates the frequency variations for process, voltage, and temperature (PVT) variations with an accuracy of ±2.6% at 2.5 GHz. ...
The DCO includes an 8 phase current-controlled ring oscillator, a digitally controlled current source (DCCS), a process and temperature (PT)counteracting voltage regulator, and a bias current generator ...
The eight-phase current controlled ring oscillator generates equally-spaced multiphase clock signals, Clkn[0:3] and Clkp[0:3], with a frequency controlled by I DCCS,INT and I DCCS,PROP . ...
doi:10.5573/jsts.2014.14.4.484
fatcat:p747mm7k3bcyxnmqjf5ssjnowe
Design of power-efficient CMOS based oscillator circuit with varactor tuning control
2021
SN Applied Sciences
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AbstractThis paper presents a low-power, wide tuning range CMOS voltage-controlled oscillator with MCML (MOS current mode logic) differential delay cell. ...
The dual control voltage of I-MOS varactor results in a tuning range from 0.528 GHz to 2.014 GHz. ...
Ring oscillator provides a wide tuning range, quadrature or multiphase output, small die area compared to LC oscillator [8] . ...
doi:10.1007/s42452-021-04501-y
fatcat:pzgyy3owmrbsnhgjx7def4bonu
DESIGN OF LOW POWER VCO ENABLED QUANTIZER IN CONTINUOUS TIME SIGMA DELTA ADC FOR SIGNAL PROCESSING APPLICATION
2016
ICTACT Journal on Microelectronics
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an added advantage of low phase noise with frequency of 100 KHz rang. ...
An accurate design of low power Voltage Controlled Oscillator (VCO) enabled quantizer in Continuous Time Sigma Delta ADC in 180nm CMOS technology using Tanner EDA tools is done. ...
While a Voltage Controlled Oscillator (VCO) based quantization which can be easily realized in a CMOS technology and can be used for high speed application [5] . ...
doi:10.21917/ijme.2016.0033
fatcat:eqpioavcybgg3iiac54q4vbj7y
An All-Digital Large-$N$ Audio Frequency Synthesizer for HDMI Applications
2012
IEEE Transactions on Circuits and Systems - II - Express Briefs
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Based on the proposed frequency search algorithm and the high-resolution digitally controlled oscillator, the frequency synthesizer cannot only provide a large frequency multiplication ratio, but it also ...
MHz) with a peak-to-peak jitter of 1.23%. ...
Thus, the proposed DCO employs a cyclic-controlled delay line (CCDL) to generate a low-frequency clock with a low hardware cost [11] . ...
doi:10.1109/tcsii.2012.2198980
fatcat:ybejyuav2beong4mzqcb6qey34
A Highly Expandable Forwarded-Clock Receiver with Ultra-Slim Data Lane using Skew Calibration by Multi-Phase Edge Monitoring
2012
JSTS Journal of Semiconductor Technology and Science
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A source-synchronous receiver based on a delay-locked loop is presented. ...
In addition, the weightadjusted dual-interpolating delay cell, which is used in the multiphase DLL, guarantees sufficient phase linearity without using dummy delay cells, while offering a high-frequency ...
With just 2 dummy delay-cells, the DLL shows a small differential nonlinearity of less than +/-0.18 LSB between its 10 phases at 3.5 GHz. ...
doi:10.5573/jsts.2012.12.4.433
fatcat:pahasjdmdjce5cqdez72jailfq
A 15-GHz CMOS Multiphase Rotary Traveling-Wave Voltage-Controlled Oscillator
2012
JSTS Journal of Semiconductor Technology and Science
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This paper presents a 15-GHz multiphase rotary traveling-wave voltage-controlled oscillator (RTW VCO) where a shielded coplanar stripline (CPS) is exploited to provide better shielding protection and lower ...
2-ps RMS clock jitter at 15 GHz. ...
INTRODUCTION Voltage-controlled oscillators (VCOs) are categorized into three distinct types by their physical mechanism: RC-based VCOs, LC-based VCOs, and transmission line (TL)-based (or wave-based) ...
doi:10.5573/jsts.2012.12.3.255
fatcat:v4wddus7x5eoln2qiif7cpm4fu
Time-Mode Analog-to-Digital Conversion Using Standard Cells
2014
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
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The proposed design is a time-mode circuit employing a voltage controlled oscillator (VCO) based multi-bit quantizer. ...
As a step towards high performance synthesizable ADCs built using generic and low accuracy components, an ADC designed exclusively with standard digital cell library components is presented. ...
The analog input is applied to a supply-controlled multiphase ring oscillator, which generates a quantized phase signal at the output. ...
doi:10.1109/tcsi.2014.2340551
fatcat:s5xv2iwcwfg43cfgca6mdv37za
Arrayable Voltage-Controlled Ring-Oscillator for Direct Time-of-Flight Image Sensors
2017
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
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A feasible approach to a compact implementation of the TDC is to use the multiple phases of a voltage-controlled ring-oscillator (VCRO) for the finest bits. ...
Direct time-of-flight (d-ToF) estimation with high frame rate requires the incorporation of a time-to-digital converter (TDC) at pixel level. ...
Specifically, tuning is achieved by connecting a variable resistor to the charging/discharging path of the individual pseudo-differential delay cell output nodes. ...
doi:10.1109/tcsi.2017.2706324
fatcat:af5fwfssobgjznr5sqmc6azece
Low-Power Programmable Pseudorandom Word Generator and Clock Multiplier Unit for High-Speed SerDes Applications
2008
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
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The measured jitter of the CMU is only 3.56 ps rms , and the data jitter at the PRWG output is mainly determined by the CMU. ...
This paper presents the design of a low-power programmable pseudorandom word generator (PRWG) and a low-noise clock multiplier unit (CMU) for high-speed SerDes applications. ...
Lownoise, low-power, and high-speed operations are achieved by 1549 utilizing a ring-type voltage-controlled oscillator (VCO) with negative skew delay compensation [13] . ...
doi:10.1109/tcsi.2008.916507
fatcat:5ifcpj2safa7xco77rt4cafn24
A 1.2-V 37–38.5-GHz Eight-Phase Clock Generator in 0.13-$\mu$m CMOS Technology
2007
IEEE Journal of Solid-State Circuits
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A 37-38.5-GHz clock generator is presented in this paper. An eight-phase voltage-controlled oscillator (VCO) is presented to generate the multiphase outputs. ...
The measured quadrature-phase outputs of VCO and input sensitivity of the divider are presented. This clock generator has been fabricated with 0.13-m CMOS technology. ...
Conventionally, the ring oscillator is widely used owing to its wideband multiphase outputs, low power, and small area. ...
doi:10.1109/jssc.2007.897169
fatcat:wpap2la3dfcw5oqiab4uhpyeda
Clocking Analysis, Implementation and Measurement Techniques for High-Speed Data Links—A Tutorial
2009
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
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Clock distribution and output waveforms with a low-swing differential input clock and inverter-driven clock tree driver. based on the normalized jitter impulse response as a function of frequency, as shown ...
These oscillators have dual controls, one with high and one with low , to maintain the wide tuning range of RC-based rings while reducing the sensitivity to bias noise from the main control loop [38] ...
doi:10.1109/tcsi.2008.931647
fatcat:m2zj3kalbvad7ee5m2znin4t7u
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