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A High-Performance Modified AXI Master Slave on-Chip Bus Design and Verification
2019
International Journal for Research in Applied Science and Engineering Technology
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This project proposes a high-performance system-on-chip bus protocol termed the AXI master-slave bus. This MSBUS is composed of a control bus (MBUS) and a data bus (SBUS). ...
Considering the inevitable tradeoff among area, throughput and energy efficiency, the control bus is developed as a low-cost and low-power bus, and the data bus is created as a high-throughput full-duplex ...
PROPOSED SYSTEM The paper titled "A High-Performance Modified AXI Master Slave On-Chip Bus Design and Verification" Proposed a highperformance system-on-chip bus protocol. ...
doi:10.22214/ijraset.2019.4376
fatcat:vaw4r6obtzap7j2umtuassbnmy
A Review of System-On-Chip Bus Protocols
English
2015
International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering
English
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A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
It gives a brief introduction of high performance system-on-chip bus protocol termed as the master-slave bus (MSBUS). ...
This paper gives a brief description of various on-chip bus protocols such as the Advanced Microcontroller Bus Architecture (AMBA) Advanced High-Performance bus (AHB) and Advanced Extensible Interface ...
core, a high-performance microprocessor, or it can be an on-chip communication subsystem such as a wrapped on-chip bus that reduces design risk, time, and manufacturing costs for SOC designs. ...
doi:10.15662/ijareeie.2015.0401042
fatcat:4noel7rqxzfanojorlsydqm7va