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Synthesis of power-optimized and area-optimized circuits from hierarchical behavioral descriptions
1998
Proceedings of the 35th annual conference on Design automation conference - DAC '98
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We present a fast and efficient algorithm for mapping multiple behaviors onto the same RTL module during the course of synthesis, thus allowing our synthesis system to explore previously unexplored regions ...
We present a technique for synthesizing power-as well as area-optimized circuits from hierarchical data flow graphs under throughput constraints. ...
Introduction High-level synthesis is the process of deriving an optimized register-transfer level (RTL) architecture from a behavioral description, usually specified as a data flow graph (DFG) for datadominated ...
doi:10.1145/277044.277167
dblp:conf/dac/LakshminarayanaJ98a
fatcat:ycml4nt5r5eedoexi6hkdl3f3e
Partitioning and optimizing controllers synthesized from hierarchical high-level descriptions
1998
Proceedings of the 35th annual conference on Design automation conference - DAC '98
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This paper describes methods for partitioning and optimizing controllers described by hierarchical high-level descriptions. ...
to control the synthesis process. ...
For example, a particular node might represent the sequencing of the sub-behaviors or the concurrent execution of the sub-behaviors, etc. ...
doi:10.1145/277044.277239
dblp:conf/dac/SeawrightM98
fatcat:f2zg4dbxrrbtjio57vqorkjiku
Resource sharing in hierarchical synthesis
1997
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97
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This paper presents a new approach to hierarchical high-level synthesis with respect to internal register-transfer structures of complex components. ...
As a result, the presented methodology offers a high degree of optimization to hierarchically specified designs. * This work is partially supported by the DFG. ent hierarchical levels, with respect to ...
A Concept for Hierarchical Synthesis In this section, we explain in more detail our hierarchical synthesis concept. First, the identification of complex components is described. ...
doi:10.1109/iccad.1997.643537
dblp:conf/iccad/BringmannR97
fatcat:wsodr5bgxnc5dhatqu3nux5aii
Survey On Scheduling And Allocation In High Level Synthesis
2012
International Journal of Computer Science & Engineering Survey
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This paper presents the detailed survey of scheduling and allocation techniques in the High Level Synthesis (HLS) presented in the research literature. ...
It also presents the methodologies and techniques to improve the Speed, (silicon) Area and Power in High Level Synthesis, which are presented in the research literature. ...
ACKNOWLEDGEMENTS We thank to the anonymous reviewers for their numerous insightful and constructive comments.
Authors Dr.M.Joseph received his PhD degree in Computer Engineering from National ...
doi:10.5121/ijcses.2012.3503
fatcat:4uehu4ufxfbmdiozesymmzavpy
A methodology and algorithms for the design of hard real-time multitasking ASICs
1999
ACM Transactions on Design Automation of Electronic Systems
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Our hierarchical approach starts from an incompletely-specified preliminary solution and uses, interchangeably, operating system and behavioral synthesis techniques to derive increasingly more detailed ...
The optimal algorithm uses several heuristics to speed up the average run time of an exhaustive branch-and-bound search. Force-directed optimization is the core of the heuristic synthesis method. ...
This design methodology is a basis for an optimal worst-case exponential time branch-and-bound synthesis algorithm as well as a fast heuristic synthesis algorithm. ...
doi:10.1145/323480.323491
fatcat:pbubnlrrmzgdnerlvg55qqapwq
Synthesis-for-testability using transformations
1995
Proceedings of the 1995 conference on Asia Pacific design automation (CD-ROM) - ASP-DAC '95
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Optimization is done using a new randomized branch and bound steepest descent algorithm. ...
We address the problem of transforming a behavioral specification so that synthesis of a testable implementation from the new specification requires significantly less area and partial scan cost than synthesis ...
synthesis system for teStability optimization). ...
doi:10.1145/224818.224961
dblp:conf/aspdac/PotkonjakDR95
fatcat:vtyplftcwjfp3h56e4nsfdozzq
Design of the Hadamard Coprocessor with the Alliance CAD System Carried by Post-Graduating Students
[chapter]
2000
Microelectronics Education
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The Choice of the Hadamard Coprocessor Although it is rarely used for image processing given its poor efficiency, this algorithm is still a very interesting example for education for various reasons. ...
A behavioral description such as Mat or Counters is directly processed by the boolean optimizer. A new behavioral description is generated and mapped by SCMAP. ...
doi:10.1007/978-94-015-9506-3_61
fatcat:zehx7jbnpbb3rhn5hv7fdzmlae
Matisse: an architectural design tool for commodity ICs
1998
IEEE Design & Test of Computers
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To implement a block in the hierarchy (for example, Data ALU in Figure 2d ) by behavioral synthesis, the designer writes the algorithmic specification in an algorithmic subset of a hardware description ...
For example, sometimes the structural design is created from a scheduled algorithmic behavior. Sometimes the schedule is created from an algorithmic behavior and a target structure. ...
doi:10.1109/54.679205
fatcat:te2s27bmtncafafa6zdorzqo4m
Architectural Synthesis with Interconnection Cost Control
[chapter]
2000
IFIP Advances in Information and Communication Technology
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Keywords: Architectural synthesis tools map algorithms to architectures under various constraints and quickly providc estimations of area and performance. ...
A way to control costly interconnections during the architcctural proccss is prcscnted in this paper. ...
A behavioral synthesis tool : GAUT The behavioral synthesis tool we use for this work is called GAUT. ...
doi:10.1007/978-0-387-35498-9_45
fatcat:4cpglcvadfhdddnboxd3jvnnyy
LLVM-C2RTL: C/C++ Based System Level RTL Design Framework Using LLVM Compiler Infrastructure
2023
IPSJ Transactions on System LSI Design Methodology
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In addition to supporting a single module generation, we extended our framework to support the hierarchical module description for efficient system design. ...
We proposed a design framework that uses the C language as a register transfer level descriptive language. ...
Figure 20 shows a simple code example for hierarchical RTL generation. ...
doi:10.2197/ipsjtsldm.16.12
fatcat:jhsink5rojgxvp7psjwrl6guje
Recent developments in high-level synthesis
1997
ACM Transactions on Design Automation of Electronic Systems
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We then describe some basic techniques for various subtasks of high-level synthesis. ...
We survey recent developments in high level synthesis technology for VLSI design. The need for higher-level design automation tools are discussed first. ...
proposed a problem-space genetic algorithm (PSGA) for datapath synthesis. ...
doi:10.1145/250243.250245
fatcat:rtry5zc5y5gjbftnhetwxvvn7a
High-Level Synthesis for Embedded Systems
[chapter]
2012
Embedded Systems - Theory and Design Methodology
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optimization algorithms. ...
First a bipartite graph is generated which contains two disjoint sets, e.g. one for variables and one for registers, or one for operations and one for functional units. ...
High-Level Synthesis for Embedded Systems, Embedded Systems -Theory and Design Methodology, Dr. ...
doi:10.5772/38370
fatcat:olgvo4yrcfa4ti37aqefduubfi
High-level Synthesis for Low-power Design
2015
IPSJ Transactions on System LSI Design Methodology
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Along this line, high-level synthesis (HLS) is a promising technology to improve design productivity and enable new opportunities for power optimization for higher design quality. ...
We provide an in-depth coverage of HLS low-power optimization techniques and synthesis algorithms proposed in the last decade. ...
Acknowledgments We thank the editorial committee for their helpful comments. ...
doi:10.2197/ipsjtsldm.8.12
fatcat:enmfcevf55bcnak3vxmlmt3eu4
Channel-based behavioral test synthesis for improved module reachability
1999
Proceedings of the conference on Design, automation and test in Europe - DATE '99
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We introduce a novel behavioral test synthesis methodology that attempts to increase module reachability, driven by powerful global design path analysis. ...
Subsequently, the proposed behavioral test synthesis scheme eliminates, during scheduling, allocation and binding, as many reachability bottlenecks, as possible. ...
synthesis optimization decisions for pathrelated design attributes, such as testability. ...
doi:10.1145/307418.307506
fatcat:z6pzt3rfsndd7probdmmxitfku
Formal ESL Synthesis for Control-Intensive Applications
2012
Advances in Software Engineering
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Then, a prototype HLS compiler tool that has been developed by the author is presented, which utilizes compiler-generators and logic programming to turn the synthesis into a formal process. ...
The focus in this work is on application-specific design, which can deliver optimal, and customized implementations, as opposed to platform or IP-based design, which is bound by the limits and constraints ...
In the synthesis algorithm, the cost function (for optimization) can be area, power, or energy. ...
doi:10.1155/2012/156907
fatcat:f55w3dv6crflzfqinksfrcahnu
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