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Architecture Support for FPGA Multi-tenancy in the Cloud
[article]
2020
arXiv
pre-print
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The proposed architecture implements a network-on-chip (NoC) designed for fast data movement and low hardware footprint. ...
Overall, our NoC interconnect achieved about 2x higher maximum frequency than the state-of-the-art and a bandwidth of 25.6 Gbps. ...
ACKNOWLEDGEMENT This work was partially supported by the ONR under the Grant CCN 0402-17643-21-0000, and the Air Force Research Lab AFRL/RIGA Cyber Assurance Branch, Rome NY. ...
arXiv:2006.08026v1
fatcat:y5xedvd7sffy3hr27z5y3dji4q
An Efficient 2D Router Architecture for Extending the Performance of Inhomogeneous 3D NoC-Based Multi-Core Architectures
2016
2016 International Symposium on Computer Architecture and High Performance Computing Workshops (SBAC-PADW)
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, alternative interconnect fabrics such as inhomogeneous three dimensional integrated Network-on-Chip (3D NoC) has emanated as a cost-effective solution for emerging multi-core design. ...
To meet the performance and scalability demands of the fast-paced technological growth towards exascale and Big-Data processing with the performance bottleneck of conventional metal based interconnects ...
To resolve this, a systematic approach for generating inhomogeneous 3D NoC architectures where the TSV and buffer utilization of the given application are exploited is proposed in [3] . ...
doi:10.1109/sbac-padw.2016.22
dblp:conf/sbac-pad/AgyemanZ16
fatcat:lpw5kwyq7zcgli5litj6dlbypu
Virtual Manycore platforms: Moving towards 100+ processor cores
2011
2011 Design, Automation & Test in Europe
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These platforms are heterogeneous, homogeneous, or a mixture of subsystems of both types, both relatively generic and quite application-specific. They are applied to many different application areas. ...
This special session deals with Manycore virtual platforms from several different perspectives, highlighting new research approaches for high speed simulation, tool and IP marketing opportunities, as well ...
The purpose of NoC virtual platform is to get the system latency for each packet, throughput for each port, utilization and contention of NoC. ...
doi:10.1109/date.2011.5763121
dblp:conf/date/LeupersEMSTC11
fatcat:tszobn6thbhmpo7b2ow37xiwoe
NOC'S: Buffered and Bufferless Structure and their design methodologies for High throughput and Low latency
2020
International Journal of Advanced Trends in Computer Science and Engineering
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To know and meet the existing issues and demands related to scalability of number of nodes, their sizes of Network on Chip (NoC) which are important networks for efficient communication to transfer multimedia ...
feasible direction finding (FDF) for switching. ...
We proposed a novel metric NC_ratio to assess the huge data stack. ...
doi:10.30534/ijatcse/2020/240932020
fatcat:kj4yllfklffqrjuaipr2c26jyy
Low power network on chip architectures: A survey
2020
Computer Science and Information Technologies
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This research mainly focusses on state-of-the-art methods for designing NoC architecture and techniques to reduce power consumption in those architectures like, network architecture, network links between ...
Mostly communication now days is done through SoC (system on chip) models so, NoC (network on chip) architecture is most appropriate solution for better performance. ...
In this paper, a force competent structure for the system on-chip (NOC) switches utilizing adaptable directing has been proposed. ...
doi:10.11591/csit.v2i3.p158-168
fatcat:rzmirvcyxfao7pu3k2nxsjmhzy
DART: A Programmable Architecture for NoC Simulation on FPGAs
2014
IEEE transactions on computers
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The increased demand for on-chip communication bandwidth as a result of the multi-core trend has made networks on-chip (NoCs) a compelling choice for the communication backbone in next-generation systems ...
To address this challenge we propose DART, a fast and flexible FPGA-based NoC simulation architecture. ...
We thank Jason Anderson and Andreas Moshovos for their feedback on this work. Additionally, we would like to thank the anonymous reviewers for their constructive suggestions. ...
doi:10.1109/tc.2012.121
fatcat:utp3dgsyrjfovogo2j3ea5ghr4
DART
2011
Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip - NOCS '11
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The increased demand for on-chip communication bandwidth as a result of the multi-core trend has made networks on-chip (NoCs) a compelling choice for the communication backbone in next-generation systems ...
To address this challenge we propose DART, a fast and flexible FPGA-based NoC simulation architecture. ...
We thank Jason Anderson and Andreas Moshovos for their feedback on this work. Additionally, we would like to thank the anonymous reviewers for their constructive suggestions. ...
doi:10.1145/1999946.1999970
dblp:conf/nocs/WangJS11
fatcat:pdsncvrtsbdwxp5udj5vhr6hi4
Design of a HW/SW communication infrastructure for a heterogeneous reconfigurable processor
2008
Proceedings of the conference on Design, automation and test in Europe - DATE '08
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Reconfigurable architectures and NoC (Network-on-Chip) have introduced new research directions for technology and flexibility issues, which have been largely investigated in the last decades. ...
The SOC integrates units of various sizes of reconfiguration granularity. The included NoC approach demonstrates the mentioned benefits and scalability for actual and future SoC design. ...
From the core/user point of view this approach describes the NoC as an enlarged and highy parallel DMA architecture. ...
doi:10.1145/1403375.1403700
fatcat:5zby5nhhtrefda7hw7fwrljo6q
The runahead network-on-chip
2016
2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)
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The Runahead NoC operates either as a power-saver to improve power-efficiency, or as an accelerator to provide ultra-low latency communication for selected packets. ...
Conventional NoCs tend to be over-provisioned for worst-case bandwidth demands. This results in ineffective use of network resources and power inefficiency. ...
A low-cost router design [37] reduces latency using a simple ring-stop inspired router architecture for fast traversal of packets travelling in one direction; packets changing direction pay additional ...
doi:10.1109/hpca.2016.7446076
dblp:conf/hpca/LiMJ16
fatcat:ix2ppbfvwfadtgp6mtsyemw3xa
Kilo-NOC
2011
SIGARCH Computer Architecture News
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Together, these techniques yield a heterogeneous Kilo-NOC architecture that consumes 45% less area and 29% less power than a state-of-the-art QOSenabled NOC without these features. ...
In response, we propose a new lightweight topology-aware QOS architecture that provides service guarantees for applications such as consolidated servers on CMPs and real-time SOCs. ...
Acknowledgments We wish to thank Naveen Muralimanohar, Emmett Witchel, and Andrew Targhetta for their contributions to this paper. ...
doi:10.1145/2024723.2000112
fatcat:vidtu6m7evc43lviuuassnggyq
Kilo-NOC
2011
Proceeding of the 38th annual international symposium on Computer architecture - ISCA '11
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Together, these techniques yield a heterogeneous Kilo-NOC architecture that consumes 45% less area and 29% less power than a state-of-the-art QOSenabled NOC without these features. ...
In response, we propose a new lightweight topology-aware QOS architecture that provides service guarantees for applications such as consolidated servers on CMPs and real-time SOCs. ...
Acknowledgments We wish to thank Naveen Muralimanohar, Emmett Witchel, and Andrew Targhetta for their contributions to this paper. ...
doi:10.1145/2000064.2000112
dblp:conf/isca/GrotHKM11
fatcat:3vveq3tdcjfxdgtfj553kjgq5i
An analysis and simulation tool of real-time communications in on-chip networks
2020
ACM SIGBED Review
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It allows fast and precise exploration of real-time design choices onto NoC architectures. ReTiNAS is an event-based simulator written in Python. ...
Further, we use ReTiNAS to perform a comparative study of analysis and simulation for different communication protocols using a wide set of synthetic experiments. ...
We would like also to aknowledge the support of Benyamina Abou Elhassen, a full professor of Oran university, for his administrative support. ...
doi:10.1145/3412821.3412822
fatcat:wz5lwujnovanrbkuguaaafdh6y
ALOE-Based Flexible LDPC Decoder
2010
2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools
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Flexible processing platforms are therefore needed for supporting multi-standard or heterogeneous radios. ...
We analyse the middleware efficiency in terms of flexibility versus resource requirements. The results show a relative middleware area overhead of 32 %. ...
ACKNOWLEDGMENT This work was supported by the European Commission in the framework of the FP7 Network of Excellence in Wireless COMmunications NEWCOM++ (contract n. 216715). ...
doi:10.1109/dsd.2010.107
dblp:conf/dsd/GomezCBMGVM10
fatcat:e57z7a4suvfxdhfrl5v4g7choe
Mapping a Pipelined Data Path onto a Network-on-Chip
2007
2007 International Symposium on Industrial Embedded Systems
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In this paper, we discuss the level of QoS needed in a specific NoC for a packet processing application. ...
Therefore, we considered to take advantage of an NoC communication architecture. A simple NoC was developed, which knowingly omits sophisticated QoS mechanisms. ...
ACKNOWLEDGMENT We thank Nokia Siemens Networks, location Greifswald, Germany, for supporting the MATMUNI project. ...
doi:10.1109/sies.2007.4297333
dblp:conf/sies/KubischCHT07
fatcat:mjezkhue35dcfftlzmro6pq5pm
Minimizing Power Consumption of Spatial Division Based Networks-on-Chip Using Multi-path and Frequency Reduction
2012
2012 15th Euromicro Conference on Digital System Design
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We propose a two-step approach by first computing the minimum feasible frequency for the entire network taking bandwidth of all connections into consideration. ...
With an increasing number of processing elements being integrated on a single die, networks-on-chip (NoCs) are emerging as a significant contributor to overall chip power consumption. ...
Note that there is no need to define an outgoing direction for the other ports, because an incoming direction from one port of a router is an outgoing direction from another port of another router. ...
doi:10.1109/dsd.2012.85
dblp:conf/dsd/WangDKC12
fatcat:vdvgkcexojandeyj62mc7nzqfm
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