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Surfing: a robust form of wave pipelining using self-timed circuit techniques
2003
Microprocessors and microsystems
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In previous wave pipelined designs, timing uncertainty grows monotonically as data propagates through gates and other logic elements. ...
Our designs propagate a timing pulse along with the data values, and our logic elements have delays that decrease in the presence of the pulse. ...
Logical effort [SSH99] is an obvious place to start. Determining a consistent effort model for preswitched gates and developing the rest of a design methodology are key areas for future work. ...
doi:10.1016/s0141-9331(03)00091-7
fatcat:gpehfqxxavhrfhum6payzr4f2q
A novel global self-timing methodology for BSFQ circuits
2003
IEEE transactions on applied superconductivity
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In this paper, we present a novel global self-timing methodology, dual encoding hierarchical pipelining (DEHP), for the locally asynchronous BSFQ circuits. ...
However, only the cell-level timing description of the BSFQ circuits was considered, which did not specify their global timing strategy in a system-level design. ...
CONCLUSION We have presented a novel global self-timing methodology, DEHP, for constructing a globally asynchronous locally asynchronous BSFQ system. ...
doi:10.1109/tasc.2003.813931
fatcat:ak2buw2cfvb5lnmb5z5zjek7q4
Self-Timed Techniques for Low-Power Digital Arithmetic in GaAs VLSI
[chapter]
2000
IFIP Advances in Information and Communication Technology
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This article presents a self-timed approach to digital Gallium Arsenide logic applicable to high performance VLSI circuits and systems. ...
The design techniques are based on GaAs Latch-Coupled FET Logic (LCFL) in order to achieve reasonable power-delay-area trade-off. ...
ACKNOWLEDGMENT The support of the Australian Research Council, German Academic Exchange Office (DAAD) and Centre for Very High Speed Microelectronic Systems at Edith Cowan University is gratefully acknowledged ...
doi:10.1007/978-0-387-35498-9_22
fatcat:xkyypitsefc3xmbpp6zc7zyhdu
Future directions in clocking multi-ghz systems
2002
Proceedings of the 2002 international symposium on Low power electronics and design - ISLPED '02
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Thus the ability to extend the operation into the time period allocated for the next pipeline stage is important. This is known as time borrowing. ...
The second part of the tutorial will address the design of such self-timed systems in which local handshaking is used to provide the necessary synchronization and sequencing of operations. ...
Thus the ability to extend the operation into the time period allocated for the next pipeline stage is important. This is known as time borrowing. ...
doi:10.1145/566461.566462
fatcat:7v3cdraysbbhneldk6pguwawq4
Future directions in clocking multi-ghz systems
2002
Proceedings of the 2002 international symposium on Low power electronics and design - ISLPED '02
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Thus the ability to extend the operation into the time period allocated for the next pipeline stage is important. This is known as time borrowing. ...
The second part of the tutorial will address the design of such self-timed systems in which local handshaking is used to provide the necessary synchronization and sequencing of operations. ...
Thus the ability to extend the operation into the time period allocated for the next pipeline stage is important. This is known as time borrowing. ...
doi:10.1145/566408.566462
dblp:conf/islped/OklobdzijaS02
fatcat:aabmzqqvfngfnbihzkrld3hr2m
The implementation of the Itanium 2 microprocessor
2002
IEEE Journal of Solid-State Circuits
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Index Terms-Clock design, computer architecture, design methodology, dynamic logic, IA-64, integrated circuit design, microprocessors. ...
The design seeks to extract maximum performance from EPIC by optimizing the memory system and execution resources for a combination of high bandwidth and low latency. ...
ACKNOWLEDGMENT The authors recognize the extraordinary efforts of a committed design team from Intel and Hewlett Packard in making the Itanium 2 processor a success. ...
doi:10.1109/jssc.2002.803943
fatcat:wvrj2j6t4rf5tdwjd5hp53s3wa
Asynchronous Design—Part 2: Systems and Methodologies
2015
IEEE design & test
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Part 2 focuses on methodologies for designing asynchronous systems, including basics of hazards, synthesis and optimization methods for both logic-level and high-level synthesis, and the development of ...
h THIS TWO-PART article aims to provide both a short historical and technical overview of asynchronous design, as well as a snapshot of the state of the art. ...
The fundamental challenge of asynchronous logic synthesis is to develop optimization techniques Editor's notes: The second part of the two-part tutorial on asynchronous design addresses methodologies for ...
doi:10.1109/mdat.2015.2413757
fatcat:bpxnljdkofh6ppyovk6sp4pknm
Berger code based concurrent online self-testing of embedded processors
2018
Journal of Semiconductors
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The proposed methodology is implemented and verified for various arithmetic and logical operations of the DLX processor. ...
The FPGA implementation of the proposed design shows that a meager increase in hardware utilization facilitates online self-testing to detect temporary faults. ...
The Berger code based totally self-checking checker (TSC) combined with two-rail checker provides a solution for the detection of temporary faults which are mainly induced by single event upset (SEU). ...
doi:10.1088/1674-4926/39/11/115001
fatcat:xmuv3fikbng6jlasxy2kqi6iay
Design and modelling of a high performance differential bipolar self-timed microprocessor
1997
IEE Proceedings - Computers and digital Techniques
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Current interest in self-timed systems is motivated by the area, power and design effort required for the global clock of VLSI synchronous designs. ...
A self-timed datapath, based on the ARM processor, using 'micropipeline' control techniques has been developed for a newly updated high performance differential bipolar technology. ...
Due to the prototype nature of the architecture, design methodology and fabrication process, an essential stage in the technology transformation was the development of a model for the self-timed microprocessor ...
doi:10.1049/ip-cdt:19971600
fatcat:27232z25anceld7gufiliwmpse
Berger Code Based Concurrent Online Self-Testing of Embedded Processors
2018
International Journal of Reconfigurable and Embedded Systems (IJRES)
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The proposed methodology is implemented and verified for various arithmetic and logical operations of the DLX processor. ...
The FPGA implementation of the proposed design shows that a meager increase in hardware utilization facilitates online self- testing to detect temporary faults. ...
The Berger code based totally self-checking checker (TSC) combined with two-rail checker provides a solution for the detection of temporary faults which are mainly induced by single event upset (SEU). ...
doi:10.11591/ijres.v7.i2.pp74-81
fatcat:wlibzdkspfga3io6x6ksltyx5m
Two FPGA Case Studies Comparing High Level Synthesis and Manual HDL for HEP applications
[article]
2018
arXiv
pre-print
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For the sorter module, the HLS version requires about 3 to 4 times more logic resources, with a slightly longer processing interval. ...
The first module is a real-time crystal identification module, and the second is a compact event timestamp sorting module. ...
For dataflow based designs such as those used in high energy physics, the HLS methodology is an appealing addition to the design toolbox. M.-A. ...
arXiv:1806.10672v1
fatcat:yiyslhxfpfc3nmuaqhxjheh3gu
A study of asynchronous design methodology for robust CMOS-nano hybrid system design
2009
ACM Journal on Emerging Technologies in Computing Systems
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A study of asynchronous design methodology for robust CMOS-nano hybrid system design. ACM ...
In this article, we analyze some of the above challenges and investigate the effectiveness of asynchronous design methodology in a hybrid system design platform using molecular crossbar and CMOS interfacing ...
In place of the traditional lithography-based "top-down" design methodology, bottom-up self-assembly based design approach appears more plausible for future nanoarchitectures. ...
doi:10.1145/1568485.1568486
fatcat:cdnngvcxcrfudf2szxltnk3z7q
Optimised asynchronous timing for superconductive digital circuits
2006
SAIEE Africa Research Journal
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Various RSFQ timing schcmcs havc bcen adaptcd from semiconduclOr design methodologies, and some have becn designed spccifically for RSFQ. ...
This paper describcs a ncw asynchronous self-liming schcmc whcre thc delails of clock distribution and clocking arc built inlo thc logic gates. ...
With careful design of the circuit logic, asynchronous self-timed pipelined clocking can be implemented. ...
doi:10.23919/saiee.2006.9487898
fatcat:fwwthjxqingb3lavliirm2poym
Efficient adders for assistive devices
2017
Engineering Science and Technology, an International Journal
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In this paper, we present a qualitative as well as a quantitative analysis of an asynchronous pipelined adder design with two latest computation completion sensing approaches based on Pseudo NMOS logic ...
Since the adder is the most widely used component in all present day assistive devices, this analysis acts as a pointer for the application of asynchronous pipelined circuits with efficient Pseudo NMOS ...
The classical dynamic pipeline -PS0 pipeline It is a self-timed pipeline sans explicit latches and is based on dynamic logic, proposed by Williams and Horowitz [19] . ...
doi:10.1016/j.jestch.2016.09.007
fatcat:m5qxne6hpzbxzeedbxvfdh3lya
Delay-insensitive gate-level pipelining
2001
Integration
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The objective of this paper is to develop and illustrate a pipelining methodology for maximizing throughput of delay-insensitive systems at the gate level. ...
Gate-Level Pipelining (GLP) techniques are developed to design throughput-optimal delay-insensitive digital systems using NULL Convention Logic (NCL). ...
Earlier work by Seitz presents an extensive discussion of self-timed logic, illustrating its advantages over traditional clocked logic, and includes one approach to designing such circuits [15] . ...
doi:10.1016/s0167-9260(01)00013-x
fatcat:e4oza2x3v5bv3bo3k3hafr5wu4
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