This device is designed and verified in a 65 nm CMOS process. With increased substrate resistance and pumped triggering current provided by power bus controlled PMOS, this structure features a significantly reduced trigger voltage of 2.8 V and an enhanced uniform conduction of multi-fingers.
A novel Substrate-Engineered Gate-Grounded NMOS (GGNMOS) structure with very low trigger voltage is proposed to protect the ultra-thin gate oxide ...
In this paper, a novel substrate-engineered GGNMOS structure with a VDD bus controlled PMOS is proposed and verified in 65 nm salicide CMOS process [11]. The ...
A novel substrate-triggered grounded-gate NMOS (GGNMOS) is verified in 65 nm CMOS silicide process. The trigger element is a PMOS controlled by the VDD bus ...
Apr 1, 2010 · A novel substrate-triggered grounded-gate NMOS (GGNMOS) is verified in 65 nm CMOS silicide process. The trigger element is a PMOS controlled ...
摘要. A novel Substrate-Engineered Gate-Grounded NMOS (GGNMOS) structure with very low trigger voltage is proposed to prote.
Dong, etl, Substrate-engineered GGNMOS for low trigger voltage ESD in 65nm CMOS process, Microelectronics Reliability, Volume 51,. Issue 12, December 2011 ...
Apr 1, 2010 · ... GGNMOS, with a 50 µm trigger ... trigger voltage ; size 65 nm. Subjects: Other ... triggered SCR with very low leakage current and adjustable ...
Substrate-engineered GGNMOS for low trigger voltage ESD in 65 nm CMOS process · Design analysis of novel substrate-triggered GGNMOS in 65nm CMOS process · RF ESD ...
