Dec 12, 2022 · Our investigation shows that PTL-based 1-bit adders achieve delay, average dynamic power, and Power-Delay-Product (PDP) reductions of up to 72.9 ...

Abstract—For the past two decades, complementary static. CMOS logic has been the dominant digital logic style because of its.

Oct 25, 2022 · In this paper, we investigate adders and multipliers circuits using Pass Transistor Logic (PTL) and demonstrate its advantages over ...

May 31, 2022 · This paper compares key performance metrics of 22 different PTL based 1-bit full adder designs to a complementary static CMOS logic reference, ...

This paper compares key performance metrics of 22 different PTL based 1-bit full adder designs to a complementary static CMOS logic reference, using a recent ...

Revisiting pass-transistor logic styles in a 12nm finfet technology node. J ... Investigation of Pass Transistor Logic in a 12nm FinFET CMOS Technology. AL ...

Comprehensive simulation results demonstrate FinFET transistors' advantage in key design metrics, including reduced dynamic power, leakage current and delay.

This paper shows that complementary CMOS is the logic style of choice for the implementation of arbitrary combinational circuits if low voltage, low power, ...

This paper examines some key issues in the implementation of SPL: swing restoration, optimum number of pass-transistor stages between buffers and SPL circuits ...