Oct 31, 2014 · Based on the proposed hybrid cache design, two access-aware policies are proposed to mitigate unbalanced wearout of the STT-RAM region, and a ...

May 2, 2013 · Experimental results show that, our proposed scheme and policies can achieve an average of 89 times improvement in cache lifetime and are able ...

High-Endurance Hybrid Cache Design in CMP Architecture with Cache Partitioning and Access-Aware Policy. Shun-Ming Syu, Yu-Hui Shao, and Ing-Chao Lin. Dept. of ...

This paper proposes a hybrid cache design that includes SRAM cache, STT-RAM cache, and STt-RAM/SRAM hybrid cache banks for CMP (chip multi-processors) ...

access-aware policies and a dynamic cache partitioning scheme. Fig. 20. Comparison of lifetime between the baseline and the proposed wear leveling scheme ...

Based on the proposed hybrid cache design, two access-aware policies are proposed to mitigate unbalanced wearout of the STT-RAM region, and a wearout-aware ...

Bibliographic details on High-endurance hybrid cache design in CMP architecture with cache partitioning and access-aware policy.

In this paper, we propose a run-time strategy for managing writes onto last level cache in chip multiprocessors where STT-RAM memory is used as baseline ...

Ing-Chao Lin*, et al., "High-Endurance Hybrid Cache Design in CMP Architecture with Cache Partitioning and Access-Aware Policies", accepted by IEEE Trans.

Jul 31, 2014 · Solved: I've just been reading this interesting paper: http://www.cs.berkeley.edu/~hcook/papers/ISCA13_Henry_Cook.pdf "A Hardware Evaluation ...