The work is designed and fabricated in SMIC 0.13 μm CMOS process, using the fully differential C-R hybrid digital to analog converter (DAC) structure. Scaling ...
The work is designed and fabricated in SMIC 0.13 μm CMOS process, using the fully differential C-R hybrid digital to analog converter (DAC) structure. Scaling ...
A capacitor-resistor DAC (C-R DAC) combined a capacitor digital-to-analog converter (CDAC) and a resistor digital-to-analog converter (RDAC) can be used to ...
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A 12-bit successive approximation register analog to digital converter (SAR ADC) built in an intelligent platform management interface (IPMI) system on chip ...
Design of a 12-bit 0.83 MS/s SAR ADC for an IPMI SoC · A 10b 200MS/s 0.82mW SAR ADC in 40nm CMOS · A Digital-Domain Calibration of Split-Capacitor DAC for a ...
An 11-bit 10 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) is proposed for low-power and small-area applications.
Design of a 12-bit 0.83 MS/s SAR ADC for an IPMI SoC. Published:2015-09 Issue: Volume: Page: ISSN: Container-title:2015 28th IEEE International System-on ...
This paper presents a successive approximation analog-to-digital converter (SAR ADC) achieving high power efficiency by adopting sub-range concept.
Nov 9, 2022 · This capacitor calibration for the CDAC requires an accurate comparator that can sense voltages less than 1 LSB without an offset voltage [16].
Oct 17, 2017 · The binary-window DAC switching scheme proposed in this paper effectively reduces DAC nonlinearity and switching errors to improve both the ...