Apr 7, 2014 · We demonstrate a hybrid (hardware-software) scheme that mitigates bit flips in data that reside in low-level caches. The methodology is shown to ...

Feb 20, 2015 · Abstract— Transient errors are a major concern for the correct operation of low-level cache memories. Aggressive integration.

The methodology is shown to be applicable in streaming applications and we illustrate that with a video decoding case study on a state-of-the-art many-core chip ...

Injected errors cause visually distorted output. ... Demonstrating HW–SW Transient Error Mitigation on the Single-Chip Cloud Computer Data Plane. Article.

Transient errors are a major concern for the correct operation of low-level cache memories. Aggressive integration requires effective mitigation of such errors, ...

Demonstrating HW–SW Transient Error Mitigation on the Single-Chip Cloud Computer Data Plane ... error rate performance and limits to the efficacy of error ...

Rodopoulos, D.; Papanikolaou, A.; Catthoor, F.; Soudris, D., "Demonstrating HW-SW Transient Error Mitigation on the Single-Chip Cloud Computer Data Plane," IEEE ...

... transient error effects in static CMOS digital circuits and will ... Demonstrating HW–SW Transient Error Mitigation on the Single-Chip Cloud Computer Data Plane.

Demonstrating HW-SW Transient Error Mitigation on the Single-Chip Cloud Computer Data Plane. D. Rodopoulos, A. Papanikolaou, F. Catthoor, and D. Soudris.

List of computer science publications by Dimitrios Rodopoulos. ... Demonstrating HW-SW Transient Error Mitigation on the Single-Chip Cloud Computer Data Plane.