Nov 26, 2014 · In this paper, a wide-range low-cost all-digital duty-cycle corrector (ADDCC) is presented. The proposed ADDCC uses a delay-recycled half-cycle ...
[PDF] A Wide-Range Low-Cost All-Digital Duty-Cycle Corrector
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All-digital duty-cycle corrector with synchronous and high accuracy output for double date rate synchronous dynamic random-access memory application · Computer ...
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Abstract— A system clock with a 50% duty cycle is demanded in high-speed data communication applications, such as double data rate memories and double ...
In this paper, a wide-range low-cost all-digital duty-cycle corrector (ADDCC) is presented. The proposed ADDCC uses a delay-recycled half-cycle time delay line ...
A wide-range all-digitalduty-cycle corrector (ADDCC) with output clock phase alignment is presented in this paper, which can correct the duty-cycle error of ...
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A wide-range all-digital duty cycle corrector (DCC) with a period monitor is presented. It corrects the duty cycle within four cycles.
This paper proposes a programmable mixed-signal DCC. The DCC is implemented in TSMC 65 nm technology. Experiment results show that proposed DCC works up to 7 ...
Apr 22, 2023 · This paper proposes a small-area and low-power all-digital duty cycle corrector with de-skew circuit. By adopting the proposed delay unit ...
This crisp presents a Modified Successive Approximation Register. (MSAR) controlled duty cycle corrector (DCC), to attain 50% duty cycle correction. Here MSAR ...
Missing: Cost | Show results with:Cost
This paper presents a duty cycle corrector (DCC) circuit for high-speed and high-precision pipelined A/D converter. Combined charge pump is used to ensure ...