Aug 11, 2014 · Our design implements a scalable 3-D-nonuniform memory access (NUMA) architecture based on low latency logarithmic interconnects, which allows ...

Abstract—Large required size, and tolerance to latency and variations in memory access time make L2 memory a suit- able option for 3-D integration.

This paper presents a synthesizable 3-D-stackable L2 memory IP component, which can be attached to a cluster-based multicore platform through its ...

This paper presents a scalable 3-D-stackable L2 memory IP component that can be attached to a cluster-based multicore platfo rm through its network-on-chip ...

Our design implements a scalable 3-D-nonuniform memory access (NUMA) architecture based on low latency logarithmic interconnects, which allows stacking of ...

Pages / Article No. 1485 - 1498. Publisher. IEEE. Subject. 3-D integration; Nonuniform memory access (NUMA); Physical implementation; Tightly coupled ...

A Modular Shared L2 Memory Design for 3-D Integration. E Azarkhish, D Rossi, I Loi, L Benini. Very Large Scale Integration (VLSI) Systems, IEEE Transactions ...

This paper presents physical-design case studies of ternary content-addressable memories (TCAMs), first-in first-out (FIFO) ... [Show full abstract] memories, ...

This redesign of the memory hierarchy truly starts with the shared L2 cache within the XCDs, but touches nearly every other aspect as well. The role of the L2 ...