Jul 29, 2014 · In this paper, we propose an efficient fault model considering the physical limitation of the devices for the PST architecture. In addition, we ...

Jan 10, 2024 · This architecture uses fine-grain redundancy, voltage scaling and timing speculation to adapt to variation and tolerate timing, soft and hard ...

The post-silicon skew tuning (PST) technique with the ability to tolerate PVT variations, even after a chip is manufactured has generated considerable ...

Mar 27, 2017 · The post-silicon skew tuning (PST) technique with the ability to tolerate PVT variations, even when a chip is manufactured has generated ...

A PST architecture can dynamically minimize the clock skew even after a chip is manufactured. However, testing the variation tolerance ability of a PST ...

Mac Y. C. Kao's 3 research works with 7 citations and 55 reads, including: A Fault Detection and Tolerance Architecture for Post-Silicon Skew Tuning.

A robust architecture for post-silicon skew tuning · Post silicon skew tuning: Survey and analysis · A Fault Detection and Tolerance Architecture for Post-Silicon ...

Mac Y. C. Kao, Kun-Ting Tsai, Shih-Chieh Chang: A Fault Detection and Tolerance Architecture for Post-Silicon Skew Tuning. IEEE Trans.

Abstract - The main objective is to detect the number of faults and to minimize the clock skew. Minimization of clock skew is quite difficult due to the PVT ...