The design is implemented in 40nm CMOS and shows that, with 1.6GHz sampling frequency, the two-step VCO-based ADC reaches 40MHz bandwidth, 59.5dB SNDR and 67.7 ...

Abstract—A two-step open-loop VCO-based ADC with 1st-order noise shaping and intrinsic nonlinearity mitigation is presented. With the open-loop structure ...

A 40MHz-BW 35fJ/step-FoM nonlinearity-cancelling two-step ADC with dual-input VCO-based quantizer · A 0.03mm2, 40nm CMOS 1.5GS/s all-digital complementary PWM- ...

The design is implemented in 40nm CMOS and shows that, with 1.6GHz sampling frequency, the two-step VCO-based ADC reaches 40MHz bandwidth, 59.5dB SNDR and 67.7 ...

The experimental results in 40 nm CMOS show that, with 1.6 GHz sampling frequency, the proposed ADC reaches 59.5 dB SNDR and 67.7 dB SFDR for 40 MHz bandwidth.

A 40 MHz-BW 10 bit two-step VCO-based Delta-Sigma ADC is presented, with the open-loop structure and highly digital building blocks, a robust performance, ...

The experimental results in 40 nm CMOS show that, with 1.6 GHz sampling frequency, the proposed ADC reaches 59.5 dB SNDR and 67.7 dB SFDR for 40 MHz bandwidth.

Conference paper Open. A 40MHz-BW two-step open-loop VCO-based ADC with 42fJ/step FoM in 40nm CMOS. Creators. Xing, Xinpeng · Gao, Peng · Gielen, Georges ...

A 40 MHz-BW 10 bit two-step VCO-based Delta-Sigma ADC is presented. With the open-loop structure and highly digital building blocks, a robust performance, ...

A 40 MHz-BW 10 bit two-step VCO-based Delta-Sigma ADC is presented. With the open-loop structure and highly digital building blocks, a robust performance, high ...